- Oct 25, 2023
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Richard Henderson authored
This will be of small comfort to sparc64, because both sun4u and sun4v board models force max_cpus = 1. But it does enable actual smp for sparc32 sun4m. Tested-by:
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by:
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Always use TSO, per the Oracle 2015 manual. This is slightly less restrictive than the TCG_MO_ALL default, and happens to match the i386 model, which will eliminate a few extra barriers on that host. Tested-by:
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by:
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Always use cpu_raise_exception_ra with GETPC for unwind. Tested-by:
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by:
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Emit the exception at the end of the translation block, so that the non-exception case can fall through. Tested-by:
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by:
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
With pairs of jmp+rett, pc == DYNAMIC_PC_LOOKUP and npc == DYNAMIC_PC. Make sure that we exit for interrupts. Cc: qemu-stable@nongnu.org Fixes: 633c4283 ("target/sparc: Introduce DYNAMIC_PC_LOOKUP") Tested-by:
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by:
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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- Oct 23, 2023
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https://gitlab.com/rth7680/qemuStefan Hajnoczi authored
tcg: Drop unused tcg_temp_free define tcg: Introduce tcg_use_softmmu tcg: Optimize past conditional branches tcg: Use constant zero when expanding with divu2 tcg: Add negsetcondi tcg: Define MO_TL tcg: Export tcg_gen_ext_{i32,i64,tl} target/*: Use tcg_gen_ext_* tcg/ppc: Enable direct branching tcg_out_goto_tb with TCG_REG_TB tcg/ppc: Use ADDPCIS for power9 tcg/ppc: Use prefixed instructions for power10 tcg/ppc: Disable TCG_REG_TB for Power9/Power10 tcg/ppc: Enable direct branching tcg_out_goto_tb with TCG_REG_TB tcg/ppc: Use ADDPCIS for power9 tcg/ppc: Use prefixed instructions for power10 tcg/ppc: Disable TCG_REG_TB for Power9/Power10 # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmU2t18dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9uXQgAhT1mDy5sg7mfSWuc # X7i54C3n6Ykyra0HDG47dt4G0gkACEs7tDkllHIxhqTPKCrzpevyZEoyigr2MEOa # 3GCwxvJORb27Ql2aiM1K8cdlEbzcrx+RZbl4lwqZpZbmMUbz/ZQI4xPEAf2yKdfB # jTzi+Iu6ziPVqVQrg6fTm1I7YgQI85qcfKxi5lBaXgSfxPXGSlLeDw9Y8QjLHXRx # nSiGpWiUd5TkqZgLIctShDbK4NEHcvjXUTW4rMWU9l5Cjdf9ZIhxcCxgKTXtOxBi # 9tUdGOiup2HudOFf+DpQorzWpwRwy3NGpUF7n+WmevQZ1Qh8uNKsveFB0uuqObLg # zlTI2Q== # =lgiT # -----END PGP SIGNATURE----- # gpg: Signature made Mon 23 Oct 2023 11:11:43 PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20231023' of https://gitlab.com/rth7680/qemu : (38 commits) target/xtensa: Use tcg_gen_sextract_i32 target/tricore: Use tcg_gen_*extract_tl target/rx: Use tcg_gen_ext_i32 target/m68k: Use tcg_gen_ext_i32 target/i386: Use tcg_gen_ext_tl target/arm: Use tcg_gen_ext_i64 tcg: Define MO_TL tcg: Export tcg_gen_ext_{i32,i64,tl} tcg: add negsetcondi target/i386: Use i128 for 128 and 256-bit loads and stores tcg: Add tcg_gen_{ld,st}_i128 tcg: Optimize past conditional branches tcg: Use constant zero when expanding with divu2 tcg: drop unused tcg_temp_free define tcg/s390x: Use tcg_use_softmmu tcg/riscv: Use tcg_use_softmmu tcg/riscv: Do not reserve TCG_GUEST_BASE_REG for guest_base zero tcg/ppc: Use tcg_use_softmmu tcg/mips: Use tcg_use_softmmu tcg/loongarch64: Use tcg_use_softmmu ... Signed-off-by:
Stefan Hajnoczi <stefanha@redhat.com>
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https://git.kernel.org/pub/scm/virt/kvm/mst/qemuStefan Hajnoczi authored
virtio,pc,pci: features, cleanups infrastructure for vhost-vdpa shadow work piix south bridge rework reconnect for vhost-user-scsi dummy ACPI QTG DSM for cxl tests, cleanups, fixes all over the place Signed-off-by:
Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmU06PMPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpNIsH/0DlKti86VZLJ6PbNqsnKxoK2gg05TbEhPZU # pQ+RPDaCHpFBsLC5qsoMJwvaEQFe0e49ZFemw7bXRzBxgmbbNnZ9ArCIPqT+rvQd # 7UBmyC+kacVyybZatq69aK2BHKFtiIRlT78d9Izgtjmp8V7oyKoz14Esh8wkE+FT # ypHUa70Addi6alNm6BVkm7bxZxi0Wrmf3THqF8ViYvufzHKl7JR5e17fKWEG0BqV # 9W7AeHMnzJ7jkTvBGUw7g5EbzFn7hPLTbO4G/VW97k0puS4WRX5aIMkVhUazsRIa # zDOuXCCskUWuRapiCwY0E4g7cCaT8/JR6JjjBaTgkjJgvo5Y8Eg= # =ILek # -----END PGP SIGNATURE----- # gpg: Signature made Sun 22 Oct 2023 02:18:43 PDT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu : (62 commits) intel-iommu: Report interrupt remapping faults, fix return value MAINTAINERS: Add include/hw/intc/i8259.h to the PC chip section vhost-user: Fix protocol feature bit conflict tests/acpi: Update DSDT.cxl with QTG DSM hw/cxl: Add QTG _DSM support for ACPI0017 device tests/acpi: Allow update of DSDT.cxl hw/i386/cxl: ensure maxram is greater than ram size for calculating cxl range vhost-user: fix lost reconnect vhost-user-scsi: start vhost when guest kicks vhost-user-scsi: support reconnect to backend vhost: move and rename the conn retry times vhost-user-common: send get_inflight_fd once hw/i386/pc_piix: Make PIIX4 south bridge usable in PC machine hw/isa/piix: Implement multi-process QEMU support also for PIIX4 hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4 hw/isa/piix: Rename functions to be shared for PCI interrupt triggering hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 hw/isa/piix: Share PIIX3's base class with PIIX4 hw/isa/piix: Harmonize names of reset control memory regions ... Signed-off-by:
Stefan Hajnoczi <stefanha@redhat.com>
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https://gitlab.com/mjt0k/qemuStefan Hajnoczi authored
trivial patches for 2023-10-21 # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEe3O61ovnosKJMUsicBtPaxppPlkFAmUzviQPHG1qdEB0bHMu # bXNrLnJ1AAoJEHAbT2saaT5ZasYH/2ex+XBdvMGU9wghGXAqPCy6NEwzSQaaPkai # xuoly0Z3vahOgJK05lXH2bQmGPP1DG8la4fv8owysteIjSncBiq8Nk9+pHylgJJj # 7eZ6BPZu+xoJRTGrBhQC5F6cCAi2YQlgGwfH+bDB4YJPm2BdYbfMuw7Wm88gVDEh # nqbU6mtV1wGaDQJtHlpJNSACxWeN6Buq5Jcj27rpeCWAGlqeJBh8qEbPgN8nDnSm # mBb3DMAWtKAZPjQLnri1MRyyXnfBavBPmeTYHz4nQQHYmeHaGw4Cez5EswnZRlau # zyMMKwYK9eo7f5mFeTr3+I6XMbiIfuICGhFwLXnNqqlgB79R9w0= # =/gNQ # -----END PGP SIGNATURE----- # gpg: Signature made Sat 21 Oct 2023 05:03:48 PDT # gpg: using RSA key 7B73BAD68BE7A2C289314B22701B4F6B1A693E59 # gpg: issuer "mjt@tls.msk.ru" # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" [full] # gpg: aka "Michael Tokarev <mjt@corpit.ru>" [full] # gpg: aka "Michael Tokarev <mjt@debian.org>" [full] # Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5 # Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931 4B22 701B 4F6B 1A69 3E59 * tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu : MAINTAINERS: Add the ompic.c file to the or1k-sim section MAINTAINERS: Fix typo in openpic_kvm.c entry MAINTAINERS: Add unvalued folders in tests/tcg/ to the right sections MAINTAINERS: Add PPC common files to PowerPC TCG CPUs MAINTAINERS: Add fw_cfg.c to PPC mac99 machine MAINTAINERS: Adjust file list for PPC pseries machine MAINTAINERS: Adjust file list for PPC e500 machines MAINTAINERS: Adjust file list for PPC 4xx CPUs MAINTAINERS: Adjust file list for PPC ref405ep machine ppc/{bamboo, virtex_ml507}: Remove useless dependency on ppc405.h header MAINTAINERS: Fix a couple s390 paths MAINTAINERS: Add docs/devel/ebpf_rss.rst to the EBPF section MAINTAINERS: Add include/hw/intc/i8259.h to the PC chip section MAINTAINERS: Add the nios2 interrupt controller to the nios2 section MAINTAINERS: Cover hw/ppc/ppc440_uc.c with Sam460ex board hw/ppc/ppc440_uc: Remove dead l2sram_update_mappings() hw/rdma/vmw/pvrdma_cmd: Use correct struct in query_port() Signed-off-by:
Stefan Hajnoczi <stefanha@redhat.com>
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https://github.com/philmd/qemuStefan Hajnoczi authored
Misc hardware patch queue - MAINTAINERS updates (Zoltan, Thomas) - Fix cutils::get_relocated_path on Windows host (Akihiko) - Housekeeping in Memory APIs (Marc-André) - SDHCI fix for SDMA transfer (Lu, Jianxian) - Various QOM/QDev/SysBus cleanups (Philippe) - Constify QemuInputHandler structure (Philippe) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmUydwwACgkQ4+MsLN6t # wN6ROw//eFpuUdzFXEp3kdZMyKkP898G3L137i5b1p6Aq5SmFoVgeAmP/pAi8FVm # yAW68BKWXcYEikGLLFcq7UCW7v+dQXAAQdQHgo+1I9QPIytuWps+v9EFiuVY8EDW # Bd7H3IfGoBHlP5IJwzgpjzR9JEN2H6aEL5mNGXEdIsShNCw7ief4vwWvFjTv/mrS # bDHg8D6yUitnHAeQv9CMLlhbZXZvZtc/qKWtJjr+w42ZiV9HrmSR3RK07ydl311k # N8z2rWbLWw2q+BhmeMnCzdSB6eUq76ZZZbMdw5M+3GQVOKW4KdPoBKBnPIDPySRK # HoULrTAgAh/ZHB6l9kltDzXPTXD4oDSme+DB/aTTqvrXG/KqXFAjgwVwPC7AzONe # adtimxBXP3EHiLh2PBGBHpCa2+FON7rD23bVbuf5G0emFydU/3sPh+gCpvdzT9oT # iUifE9WstZg1tPvrRqwf8xoDXVx0f2v+h7V4WOoVWygYbA+1PkRImzsHcqqpOKYS # YLP857mtDYzL1xhW8gdwn4Zkmj6E6irICHbd4HDh5VQJMy8dQoUMT3DlxUPUOriW # vitoLJTvk6yHfUODXFcvs34wEgPGGlM5WM9qh2J0tpjUR6st/6tTTxZUkQ8a5QjM # q6+YZ85ZwtP3Eax16Re5hwcI1VrRyv/YdFQmTuiW1dQPGgQV+/8= # =KiWh # -----END PGP SIGNATURE----- # gpg: Signature made Fri 20 Oct 2023 05:48:12 PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20231020' of https://github.com/philmd/qemu : (41 commits) ui/input: Constify QemuInputHandler structure hw/net: Declare link using static DEFINE_PROP_LINK() macro hw/dma: Declare link using static DEFINE_PROP_LINK() macro hw/scsi/virtio-scsi: Use VIRTIO_SCSI_COMMON() macro hw/display/virtio-gpu: Use VIRTIO_DEVICE() macro hw/block/vhost-user-blk: Use DEVICE() / VIRTIO_DEVICE() macros hw/virtio/virtio-pmem: Replace impossible check by assertion hw/s390x/css-bridge: Realize sysbus device before accessing it hw/isa: Realize ISA bridge device before accessing it hw/arm/virt: Realize ARM_GICV2M sysbus device before accessing it hw/acpi: Realize ACPI_GED sysbus device before accessing it hw/pci-host/bonito: Do not use SysBus API to map local MMIO region hw/misc/allwinner-dramc: Do not use SysBus API to map local MMIO region hw/misc/allwinner-dramc: Move sysbus_mmio_map call from init -> realize hw/i386/intel_iommu: Do not use SysBus API to map local MMIO region hw/i386/amd_iommu: Do not use SysBus API to map local MMIO region hw/intc/spapr_xive: Do not use SysBus API to map local MMIO region hw/intc/spapr_xive: Move sysbus_init_mmio() calls around hw/ppc/pnv: Do not use SysBus API to map local MMIO region hw/ppc/pnv_xscom: Do not use SysBus API to map local MMIO region ... Signed-off-by:
Stefan Hajnoczi <stefanha@redhat.com>
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- Oct 22, 2023
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Richard Henderson authored
Reviewed-by:
Max Filippov <jcmvbkbc@gmail.com> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
The EXTR instructions can use the extract opcodes. Reviewed-by:
Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Reviewed-by:
Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
We still need to check OS_{BYTE,WORD,LONG}, because m68k includes floating point in OS_*. Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
The ext_and_shift_reg helper does this plus a shift. The non-zero check for shift count is duplicate to the one done within tcg_gen_shli_i64. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Paolo Bonzini authored
This will also come in handy later for "less than" comparisons. Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com> Message-Id: <03ba02fd-fade-4409-be16-2f81a5690b4c@redhat.com> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
The two concrete type functions already existed, merely needing a bit of hardening to invalid inputs. Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Paolo Bonzini authored
This can be useful to write a shift bit extraction that does not depend on TARGET_LONG_BITS. Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20231019104648.389942-15-pbonzini@redhat.com> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Do not require the translators to jump through concat and extract of i64 in order to move values to and from env. Tested-by:
Song Gao <gaosong@loongson.cn> Reviewed-by:
Song Gao <gaosong@loongson.cn> Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
We already register allocate through extended basic blocks, optimize through extended basic blocks as well. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Mike Frysinger authored
Use of the API was removed a while back, but the define wasn't. Signed-off-by:
Mike Frysinger <vapier@gentoo.org> Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231015010046.16020-1-vapier@gentoo.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Fixes: 92c041c5 ("tcg/riscv: Add the prologue generation and register the JIT") Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Fix TCG_GUEST_BASE_REG to use 'TCG_REG_R30' instead of '30'. Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Provide a define to allow !tcg_use_softmmu code paths to compile in system mode, but require elimination. Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Begin disconnecting CONFIG_SOFTMMU from !CONFIG_USER_ONLY. Introduce a variable which can be set at startup to select one method or another for user-only. Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
This appears to slightly improve performance on power9/10. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
The prefixed instructions have a pc-relative form to use here. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
The prefixed instruction has a pc-relative form to use here. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
When the offset is out of range of the non-prefixed insn, but fits the 34-bit immediate of the prefixed insn, use that. Reviewed-by:
Jordan Niethe <jniethe5@gmail.com> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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Richard Henderson authored
PADDI can load 34-bit immediates and 34-bit pc-relative addresses. Reviewed-by:
Jordan Niethe <jniethe5@gmail.com> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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