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  1. Oct 02, 2020
  2. Oct 01, 2020
    • Peter Maydell's avatar
      Merge remote-tracking branch 'remotes/jsnow-gitlab/tags/ide-pull-request' into staging · b5ce42f5
      Peter Maydell authored
      
      Pull request
      
      # gpg: Signature made Thu 01 Oct 2020 18:41:05 BST
      # gpg:                using RSA key F9B7ABDBBCACDF95BE76CBD07DEF8106AAFC390E
      # gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" [full]
      # Primary key fingerprint: FAEB 9711 A12C F475 812F  18F2 88A9 064D 1835 61EB
      #      Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76  CBD0 7DEF 8106 AAFC 390E
      
      * remotes/jsnow-gitlab/tags/ide-pull-request:
        ide: cancel pending callbacks on SRST
        ide: clear interrupt on command write
        ide: remove magic constants from the device register
        ide: reorder set/get sector functions
        ide: model HOB correctly
        ide: don't tamper with the device register
        ide: rename cmd_write to ctrl_write
        hw/ide/ahci: Do not dma_memory_unmap(NULL)
        MAINTAINERS: Update my git address
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      b5ce42f5
    • John Snow's avatar
      ide: cancel pending callbacks on SRST · 55adb3c4
      John Snow authored
      
      The SRST implementation did not keep up with the rest of IDE; it is
      possible to perform a weak reset on an IDE device to remove the BSY/DRQ
      bits, and then issue writes to the control/device registers which can
      cause chaos with the state machine.
      
      Fix that by actually performing a real reset.
      
      Reported-by: default avatarAlexander Bulekov <alxndr@bu.edu>
      Fixes: https://bugs.launchpad.net/qemu/+bug/1878253
      Fixes: https://bugs.launchpad.net/qemu/+bug/1887303
      Fixes: https://bugs.launchpad.net/qemu/+bug/1887309
      
      
      Signed-off-by: default avatarJohn Snow <jsnow@redhat.com>
      55adb3c4
    • John Snow's avatar
      ide: clear interrupt on command write · 6f52e69f
      John Snow authored
      
      Not known to fix any bug, but I couldn't help but notice that ATA
      specifies that writing to this register should clear an interrupt.
      
      ATA7: Section 5.3.3 (Command register - Effect)
      ATA6: Section 7.4.4 (Command register - Effect)
      ATA5: Section 7.4.4 (Command register - Effect)
      ATA4: Section 7.4.4 (Command register - Effect)
      ATA3: Section 5.2.2 (Command register)
      
      Other editions: try searching for the phrase "Writing this register".
      
      Signed-off-by: default avatarJohn Snow <jsnow@redhat.com>
      6f52e69f
    • John Snow's avatar
      ide: remove magic constants from the device register · 0c7515e1
      John Snow authored
      
      (In QEMU, we call this the "select" register.)
      
      My memory isn't good enough to memorize what these magic runes
      do. Label them to prevent mixups from happening in the future.
      
      Side note: I assume it's safe to always set 0xA0 even though ATA2 claims
      these bits are reserved, because ATA3 immediately reinstated that these
      bits should be always on. ATA4 and subsequent specs only claim that the
      fields are obsolete, so I assume it's safe to leave these set and that
      it should work with the widest array of guests.
      
      Signed-off-by: default avatarJohn Snow <jsnow@redhat.com>
      0c7515e1
    • John Snow's avatar
      ide: reorder set/get sector functions · 14ee9b53
      John Snow authored
      
      Reorder these just a pinch to make them more obvious at a glance what
      the addressing mode is.
      
      Signed-off-by: default avatarJohn Snow <jsnow@redhat.com>
      Reviewed-by: default avatarPhilippe Mathieu-Daudé <philmd@redhat.com>
      14ee9b53
    • John Snow's avatar
      ide: model HOB correctly · be8c9423
      John Snow authored
      
      I have been staring at this FIXME for years and I never knew what it
      meant. I finally stumbled across it!
      
      When writing to the command registers, the old value is shifted into a
      HOB copy of the register and the new value is written into the primary
      register. When reading registers, the value retrieved is dependent on
      the HOB bit in the CONTROL register.
      
      By setting bit 7 (0x80) in CONTROL, any register read will, if it has
      one, yield the HOB value for that register instead.
      
      Our code has a problem: We were using bit 7 of the DEVICE register to
      model this. We use bus->cmd roughly as the control register already, as
      it stores the value from ide_ctrl_write.
      
      Lastly, all command register writes reset the HOB, so fix that, too.
      
      Signed-off-by: default avatarJohn Snow <jsnow@redhat.com>
      be8c9423
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