- Mar 05, 2020
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Palmer Dabbelt authored
This would almost certainly cause the exception names to be reported incorrectly. Coverity found the issue (CID 1420223). As per Peter's suggestion, I've also added a comma at the end of the list to avoid the issue reappearing in the future. Fixes: ab67a1d0 ("target/riscv: Add support for the new execption numbers") Reviewed-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by:
Palmer Dabbelt <palmerdabbelt@google.com>
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Peter Maydell authored
* versal: Implement ADMA * Implement (trivially) ARMv8.2-TTCNP * hw/arm/smmu-common: a fix to smmu_find_smmu_pcibus * Remove unnecessary endianness-handling on some boards * Avoid minor memory leaks from timer_new in some devices * Honour more of the HCR_EL2 trap bits * Complain rather than ignoring bad command line options for cubieboard * Honour TBI for DC ZVA and exception return # gpg: Signature made Thu 05 Mar 2020 16:30:17 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200305: (37 commits) target/arm: Clean address for DC ZVA target/arm: Use DEF_HELPER_FLAGS for helper_dc_zva target/arm: Move helper_dc_zva to helper-a64.c target/arm: Apply TBI to ESR_ELx in helper_exception_return target/arm: Introduce core_to_aa64_mmu_idx target/arm: Optimize cpu_mmu_index target/arm: Replicate TBI/TBID bits for single range regimes hw/arm/cubieboard: report error when using unsupported -bios argument hw/arm/cubieboard: restrict allowed RAM size to 512MiB and 1GiB hw/arm/cubieboard: restrict allowed CPU type to ARM Cortex-A8 hw/arm/cubieboard: use ARM Cortex-A8 as the default CPU in machine definition tests/tcg/aarch64: Add newline in pauth-1 printf target/arm: Honor the HCR_EL2.TTLB bit target/arm: Honor the HCR_EL2.TPU bit target/arm: Honor the HCR_EL2.TPCP bit target/arm: Honor the HCR_EL2.TACR bit target/arm: Honor the HCR_EL2.TSW bit target/arm: Honor the HCR_EL2.{TVM,TRVM} bits target/arm: Improve masking in arm_hcr_el2_eff target/arm: Remove EL2 and EL3 setup from user-only ... Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored
This data access was forgotten when we added support for cleaning addresses of TBI information. Fixes: 3a471103 Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20200302175829.2183-8-richard.henderson@linaro.org Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored
The function does not write registers, and only reads them by implication via the exception path. Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Reviewed-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200302175829.2183-7-richard.henderson@linaro.org Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored
This is an aarch64-only function. Move it out of the shared file. This patch is code movement only. Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Reviewed-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200302175829.2183-6-richard.henderson@linaro.org Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored
We missed this case within AArch64.ExceptionReturn. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Message-id: 20200302175829.2183-5-richard.henderson@linaro.org Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored
If by context we know that we're in AArch64 mode, we need not test for M-profile when reconstructing the full ARMMMUIdx. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Reviewed-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Message-id: 20200302175829.2183-4-richard.henderson@linaro.org Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored
We now cache the core mmu_idx in env->hflags. Rather than recompute from scratch, extract the field. All of the uses of cpu_mmu_index within target/arm are within helpers, and env->hflags is always stable within a translation block from whence helpers are called. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Message-id: 20200302175829.2183-3-richard.henderson@linaro.org Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored
Replicate the single TBI bit from TCR_EL2 and TCR_EL3 so that we can unconditionally use pointer bit 55 to index into our composite TBI1:TBI0 field. Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Reviewed-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200302175829.2183-2-richard.henderson@linaro.org Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Niek Linnenbank authored
The Cubieboard machine does not support the -bios argument. Report an error when -bios is used and exit immediately. Signed-off-by:
Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20200227220149.6845-5-nieklinnenbank@gmail.com Reviewed-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Niek Linnenbank authored
The Cubieboard contains either 512MiB or 1GiB of onboard RAM [1]. Prevent changing RAM to a different size which could break user programs. [1] http://linux-sunxi.org/Cubieboard Signed-off-by:
Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20200227220149.6845-4-nieklinnenbank@gmail.com Reviewed-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Niek Linnenbank authored
The Cubieboard has an ARM Cortex-A8. Instead of simply ignoring a bogus -cpu option provided by the user, give them an error message so they know their command line is wrong. Signed-off-by:
Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20200227220149.6845-3-nieklinnenbank@gmail.com Reviewed-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> [PMM: tweaked commit message] Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Niek Linnenbank authored
The Cubieboard is a singleboard computer with an Allwinner A10 System-on-Chip [1]. As documented in the Allwinner A10 User Manual V1.5 [2], the SoC has an ARM Cortex-A8 processor. Currently the Cubieboard machine definition specifies the ARM Cortex-A9 in its description and as the default CPU. This patch corrects the Cubieboard machine definition to use the ARM Cortex-A8. The only user-visible effect is that our textual description of the machine was wrong, because hw/arm/allwinner-a10.c always creates a Cortex-A8 CPU regardless of the default value in the MachineClass struct. [1] http://docs.cubieboard.org/products/start#cubieboard1 [2] https://linux-sunxi.org/File:Allwinner_A10_User_manual_V1.5.pdf Fixes: 8a863c81 Signed-off-by:
Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20200227220149.6845-2-nieklinnenbank@gmail.com Reviewed-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> [note in commit message that the bug didn't have much visible effect] Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored
Make the output just a bit prettier when running by hand. Cc: Alex Bennée <alex.bennee@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-13-richard.henderson@linaro.org Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored
This bit traps EL1 access to tlb maintenance insns. Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-12-richard.henderson@linaro.org Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored
This bit traps EL1 access to cache maintenance insns that operate to the point of unification. There are no longer any references to plain aa64_cacheop_access, so remove it. Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-11-richard.henderson@linaro.org Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored
This bit traps EL1 access to cache maintenance insns that operate to the point of coherency or persistence. Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-10-richard.henderson@linaro.org Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored
This bit traps EL1 access to the auxiliary control registers. Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-9-richard.henderson@linaro.org Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored
These bits trap EL1 access to set/way cache maintenance insns. Buglink: https://bugs.launchpad.net/bugs/1863685 Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-8-richard.henderson@linaro.org Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored
These bits trap EL1 access to various virtual memory controls. Buglink: https://bugs.launchpad.net/bugs/1855072 Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-7-richard.henderson@linaro.org Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored
Update the {TGE,E2H} == '11' masking to ARMv8.6. If EL2 is configured for aarch32, disable all of the bits that are RES0 in aarch32 mode. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-6-richard.henderson@linaro.org Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored
We have disabled EL2 and EL3 for user-only, which means that these registers "don't exist" and should not be set. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-5-richard.henderson@linaro.org Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored
In arm_cpu_reset, we configure many system registers so that user-only behaves as it should with a minimum of ifdefs. However, we do not set all of the system registers as required for a cpu with EL2 and EL3. Disabling EL2 and EL3 mean that we will not look at those registers, which means that we don't have to worry about configuring them. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-4-richard.henderson@linaro.org Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-3-richard.henderson@linaro.org Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored
Don't merely start with v8.0, handle v7VE as well. Ensure that writes from aarch32 mode do not change bits in the other half of the register. Protect reads of aa64 id registers with ARM_FEATURE_AARCH64. Suggested-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-2-richard.henderson@linaro.org Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Pan Nengyuan authored
There are some memleaks when we call 'device_list_properties'. This patch move timer_new from init into realize to fix it. Reported-by:
Euler Robot <euler.robot@huawei.com> Signed-off-by:
Pan Nengyuan <pannengyuan@huawei.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com> Message-id: 20200227025055.14341-7-pannengyuan@huawei.com Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Pan Nengyuan authored
There are some memleaks when we call 'device_list_properties'. This patch move timer_new from init into realize to fix it. Reported-by:
Euler Robot <euler.robot@huawei.com> Signed-off-by:
Pan Nengyuan <pannengyuan@huawei.com> Message-id: 20200227025055.14341-5-pannengyuan@huawei.com Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Pan Nengyuan authored
There are some memleaks when we call 'device_list_properties'. This patch move timer_new from init into realize to fix it. Reported-by:
Euler Robot <euler.robot@huawei.com> Signed-off-by:
Pan Nengyuan <pannengyuan@huawei.com> Message-id: 20200227025055.14341-4-pannengyuan@huawei.com Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Pan Nengyuan authored
There are some memleaks when we call 'device_list_properties'. This patch move timer_new from init into realize to fix it. Reported-by:
Euler Robot <euler.robot@huawei.com> Signed-off-by:
Pan Nengyuan <pannengyuan@huawei.com> Message-id: 20200227025055.14341-3-pannengyuan@huawei.com Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Philippe Mathieu-Daudé authored
We only build the little-endian softmmu configurations. Checking for big endian is pointless, remove the unused code. Signed-off-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Philippe Mathieu-Daudé authored
We only build the little-endian softmmu configurations. Checking for big endian is pointless, remove the unused code. Signed-off-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Philippe Mathieu-Daudé authored
We only build the little-endian softmmu configurations. Checking for big endian is pointless, remove the unused code. Signed-off-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Philippe Mathieu-Daudé authored
We only build the little-endian softmmu configurations. Checking for big endian is pointless, remove the unused code. Signed-off-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Philippe Mathieu-Daudé authored
As the Connex and Verdex machines only boot in little-endian, we can simplify the code. Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Philippe Mathieu-Daudé authored
The smmu_find_smmu_pcibus() function was introduced (in commit cac994ef) in a code format that could return an incorrect pointer, which was then fixed by the previous commit. We could have avoided this by writing the if() statement differently. Do it now, in case this function is re-used. The code is easier to review (harder to miss bugs). Acked-by:
Eric Auger <eric.auger@redhat.com> Reviewed-by:
Peter Xu <peterx@redhat.com> Signed-off-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Eric Auger authored
Make sure a null SMMUPciBus is returned in case we were not able to identify a pci bus matching the @bus_num. This matches the fix done on intel iommu in commit: a2e1cd41 Signed-off-by:
Eric Auger <eric.auger@redhat.com> Reviewed-by:
Peter Xu <peterx@redhat.com> Message-Id: <20200226172628.17449-1-eric.auger@redhat.com> Reviewed-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Peter Maydell authored
The ARMv8.2-TTCNP extension allows an implementation to optimize by sharing TLB entries between multiple cores, provided that software declares that it's ready to deal with this by setting a CnP bit in the TTBRn_ELx. It is mandatory from ARMv8.2 onward. For QEMU's TLB implementation, sharing TLB entries between different cores would not really benefit us and would be a lot of work to implement. So we implement this extension in the "trivial" manner: we allow the guest to set and read back the CnP bit, but don't change our behaviour (this is an architecturally valid implementation choice). The only code path which looks at the TTBRn_ELx values for the long-descriptor format where the CnP bit is defined is already doing enough masking to not get confused when the CnP bit at the bottom of the register is set, so we can simply add a comment noting why we're relying on that mask. Signed-off-by:
Peter Maydell <peter.maydell@linaro.org> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20200225193822.18874-1-peter.maydell@linaro.org
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Edgar E. Iglesias authored
Generate xlnx-versal-virt zdma FDT nodes. Signed-off-by:
Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by:
Francisco Iglesias <frasse.iglesias@gmail.com> Reviewed-by:
KONRAD Frederic <frederic.konrad@adacore.com> Reviewed-by:
Luc Michel <luc.michel@greensocs.com> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Edgar E. Iglesias authored
Add support for the Versal LPD ADMAs. Signed-off-by:
Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by:
Francisco Iglesias <frasse.iglesias@gmail.com> Reviewed-by:
KONRAD Frederic <frederic.konrad@adacore.com> Reviewed-by:
Luc Michel <luc.michel@greensocs.com> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Peter Maydell authored
QAPI patches for 2020-03-05 # gpg: Signature made Thu 05 Mar 2020 12:42:15 GMT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-qapi-2020-03-05: qapi: Brush off some (py)lint qapi: Use super() now we have Python 3 qapi: Drop conditionals for Python 2 qapi: Inheriting from object is pointless with Python 3, drop Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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