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  1. Jan 12, 2022
    • Daniel Henrique Barboza's avatar
      ppc/pnv: turn 'phb' into a pointer in struct PnvPhb4PecStack · dc8e2914
      Daniel Henrique Barboza authored
      
      At this moment, stack->phb is the plain PnvPHB4 device itself instead of
      a pointer to the device. This will present a problem when adding user
      creatable devices because we can't deal with this struct and the
      realize() callback from the user creatable device.
      
      We can't get rid of this attribute, similar to what we did when enabling
      pnv-phb3 user creatable devices, because pnv_phb4_update_regions() needs
      to access stack->phb to do its job. This function is called twice in
      pnv_pec_stk_update_map(), which is one of the nested xscom write
      callbacks (via pnv_pec_stk_nest_xscom_write()). In fact,
      pnv_pec_stk_update_map() code comment is explicit about how the order of
      the unmap/map operations relates with the PHB subregions.
      
      All of this indicates that this code is tied together in a way that we
      either go on a crusade, featuring lots of refactories and redesign and
      considerable pain, to decouple stack and phb mapping, or we allow stack
      update_map operations to access the associated PHB as it is today even
      after introducing pnv-phb4 user devices.
      
      This patch chooses the latter. Instead of getting rid of stack->phb,
      turn it into a PHB pointer. This will allow us to assign an user created
      PHB to an existing stack later. In this process,
      pnv_pec_stk_instance_init() is removed because stack->phb is being
      initialized in stk_realize() instead.
      
      Reviewed-by: default avatarCédric Le Goater <clg@kaod.org>
      Signed-off-by: default avatarDaniel Henrique Barboza <danielhb413@gmail.com>
      Message-Id: <20220111131027.599784-4-danielhb413@gmail.com>
      Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
      dc8e2914
    • Daniel Henrique Barboza's avatar
      pnv_phb4_pec.c: move pnv_pec_phb_offset() to pnv_phb4.c · 5032f5d7
      Daniel Henrique Barboza authored
      
      The logic inside pnv_pec_phb_offset() will be useful in the next patch
      to determine the stack that should contain a PHB4 device.
      
      Move the function to pnv_phb4.c and make it public since there's no
      pnv_phb4_pec.h header. While we're at it, add 'stack_index' as a
      parameter and make the function return 'phb-id' directly. And rename it
      to pnv_phb4_pec_get_phb_id() to be even clearer about the function
      intent.
      
      Reviewed-by: default avatarCédric Le Goater <clg@kaod.org>
      Signed-off-by: default avatarDaniel Henrique Barboza <danielhb413@gmail.com>
      Message-Id: <20220110143346.455901-3-danielhb413@gmail.com>
      Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
      5032f5d7
    • Daniel Henrique Barboza's avatar
      pnv_phb4.c: change TYPE_PNV_PHB4_ROOT_BUS name · 45157581
      Daniel Henrique Barboza authored
      
      Similar to what was happening with pnv-phb3 buses,
      TYPE_PNV_PHB4_ROOT_BUS set to "pnv-phb4-root-bus" is a bit too long for
      a default root bus name. The usual default name for theses buses in QEMU
      are 'pcie', but we want to make a distinction between pnv-phb4 buses and
      other PCIE buses, at least as far as default name goes, because not all
      PCIE devices are attachable to a pnv-phb4 root-bus type.
      
      Changing the default to 'pnv-phb4-root' allow us to have a shorter name
      while making this bus distinct, and the user can always set its own bus
      naming via the "id" attribute anyway.
      
      This is the 'info qtree' output after this change, using a powernv9
      domain with 2 sockets and default settings enabled:
      
      qemu-system-ppc64 -m 4G -machine powernv9,accel=tcg \
           -smp 2,sockets=2,cores=1,threads=1
      
        dev: pnv-phb4, id ""
          index = 5 (0x5)
          chip-id = 1 (0x1)
          version = 704374636546 (0xa400000002)
          device-id = 1217 (0x4c1)
          x-config-reg-migration-enabled = true
          bypass-iommu = false
          bus: pnv-phb4-root.11
            type pnv-phb4-root
            dev: pnv-phb4-root-port, id ""
      (...)
        dev: pnv-phb4, id ""
          index = 0 (0x0)
          chip-id = 1 (0x1)
          version = 704374636546 (0xa400000002)
          device-id = 1217 (0x4c1)
          x-config-reg-migration-enabled = true
          bypass-iommu = false
          bus: pnv-phb4-root.6
            type pnv-phb4-root
            dev: pnv-phb4-root-port, id ""
      (..)
        dev: pnv-phb4, id ""
          index = 5 (0x5)
          chip-id = 0 (0x0)
          version = 704374636546 (0xa400000002)
          device-id = 1217 (0x4c1)
          x-config-reg-migration-enabled = true
          bypass-iommu = false
          bus: pnv-phb4-root.5
            type pnv-phb4-root
            dev: pnv-phb4-root-port, id ""
      (...)
        dev: pnv-phb4, id ""
          index = 0 (0x0)
          chip-id = 0 (0x0)
          version = 704374636546 (0xa400000002)
          device-id = 1217 (0x4c1)
          x-config-reg-migration-enabled = true
          bypass-iommu = false
          bus: pnv-phb4-root.0
            type pnv-phb4-root
            dev: pnv-phb4-root-port, id ""
      
      Reviewed-by: default avatarCédric Le Goater <clg@kaod.org>
      Signed-off-by: default avatarDaniel Henrique Barboza <danielhb413@gmail.com>
      Message-Id: <20220110143346.455901-11-danielhb413@gmail.com>
      Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
      45157581
    • Daniel Henrique Barboza's avatar
      pnv_phb3.h: change TYPE_PNV_PHB3_ROOT_BUS name · 41cb8d31
      Daniel Henrique Barboza authored
      
      The TYPE_PNV_PHB3_ROOT_BUS name is used as the default bus name when
      the dev has no 'id'. However, pnv-phb3-root-bus is a bit too long to be
      used as a bus name.
      
      Most common QEMU buses and PCI controllers are named based on their bus
      type (e.g. pSeries spapr-pci-host-bridge is called 'pci'). The most
      common name for a PCIE bus controller in QEMU is 'pcie'. Naming it
      'pcie' would break the documented use of the pnv-phb3 device, since
      'pcie.0' would now refer to the root bus instead of the first root port.
      
      There's nothing particularly wrong with the 'root-bus' name used before,
      aside from the fact that 'root-bus' is being used for pnv-phb3 and
      pnv-phb4 created buses, which is not quite correct since these buses
      aren't implemented the same way in QEMU - you can't plug a
      pnv-phb4-root-port into a pnv-phb3 root bus, for example.
      
      This patch renames it as 'pnv-phb3-root', which is a compromise between
      the existing and the previously used name. Creating 3 phbs without ID
      will result in an "info qtree" output similar to this:
      
      bus: main-system-bus
        type System
        dev: pnv-phb3, id ""
          index = 2 (0x2)
          chip-id = 0 (0x0)
          x-config-reg-migration-enabled = true
          bypass-iommu = false
          bus: pnv-phb3-root.2
            type pnv-phb3-root
      (...)
        dev: pnv-phb3, id ""
          index = 1 (0x1)
          chip-id = 0 (0x0)
          x-config-reg-migration-enabled = true
          bypass-iommu = false
          bus: pnv-phb3-root.1
            type pnv-phb3-root
      (...)
        dev: pnv-phb3, id ""
          index = 0 (0x0)
          chip-id = 0 (0x0)
          x-config-reg-migration-enabled = true
          bypass-iommu = false
          bus: pnv-phb3-root.0
            type pnv-phb3-root
      
      Signed-off-by: default avatarDaniel Henrique Barboza <danielhb413@gmail.com>
      Message-Id: <20220105212338.49899-11-danielhb413@gmail.com>
      Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
      41cb8d31
    • Cédric Le Goater's avatar
      ppc/pnv: Move num_phbs under Pnv8Chip · eb93c828
      Cédric Le Goater authored
      
      It is not used elsewhere so that's where it belongs.
      
      Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
      Message-Id: <20220105212338.49899-10-danielhb413@gmail.com>
      Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
      eb93c828
    • Cédric Le Goater's avatar
      ppc/pnv: Reparent user created PHB3 devices to the PnvChip · c29dd003
      Cédric Le Goater authored
      
      The powernv machine uses the object hierarchy to populate the device
      tree and each device should be parented to the chip it belongs to.
      This is not the case for user created devices which are parented to
      the container "/unattached".
      
      Make sure a PHB3 device is parented to its chip by reparenting the
      object if necessary.
      
      Reviewed-by: default avatarDaniel Henrique Barboza <danielhb413@gmail.com>
      Reviewed-by: default avatarFrederic Barrat <fbarrat@linux.ibm.com>
      Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
      Message-Id: <20220105212338.49899-8-danielhb413@gmail.com>
      Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
      c29dd003
    • Cédric Le Goater's avatar
      ppc/pnv: Introduce support for user created PHB3 devices · 1f6a88ff
      Cédric Le Goater authored
      
      PHB3 devices and PCI devices can now be added to the powernv8 machine
      using :
      
        -device pnv-phb3,chip-id=0,index=1 \
        -device nec-usb-xhci,bus=pci.1,addr=0x0
      
      The 'index' property identifies the PHB3 in the chip. In case of user
      created devices, a lookup on 'chip-id' is required to assign the
      owning chip.
      
      Reviewed-by: default avatarDaniel Henrique Barboza <danielhb413@gmail.com>
      Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
      Message-Id: <20220105212338.49899-7-danielhb413@gmail.com>
      Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
      1f6a88ff
    • Daniel Henrique Barboza's avatar
      pnv_phb4.c: make pnv-phb4-root-port user creatable · 1360fd83
      Daniel Henrique Barboza authored
      
      We want to create only the absolutely minimal amount of devices when
      running with -nodefaults. The root port is something that the machine
      can boot up without. But, to do that, we need to provide a way for the
      user to add them by hand.
      
      This patch makes pnv-phb4-root-port user creatable and then uses the
      pnv_phb_attach_root_port() helper to add a pnv_phb4_root_port only when
      running with default settings.
      
      Signed-off-by: default avatarDaniel Henrique Barboza <danielhb413@gmail.com>
      Message-Id: <20220105212338.49899-5-danielhb413@gmail.com>
      Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
      1360fd83
    • Cédric Le Goater's avatar
      ppc/pnv: Attach PHB3 root port device when defaults are enabled · a71cd51e
      Cédric Le Goater authored
      
      This cleanups the PHB3 model a bit more since the root port is an
      independent device and it will ease our task when adding user created
      PHB3s.
      
      pnv_phb_attach_root_port() is made public in pnv.c so it can be reused
      with the pnv_phb4 root port later.
      
      Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
      Signed-off-by: default avatarDaniel Henrique Barboza <danielhb413@gmail.com>
      Message-Id: <20220105212338.49899-4-danielhb413@gmail.com>
      Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
      a71cd51e
  2. Jan 10, 2022
  3. Jan 08, 2022
  4. Jan 07, 2022
  5. Jan 06, 2022
  6. Jan 05, 2022
  7. Jan 04, 2022
  8. Dec 31, 2021
    • Yanan Wang's avatar
      hw/core/machine: Introduce CPU cluster topology support · 864c3b5c
      Yanan Wang authored
      
      The new Cluster-Aware Scheduling support has landed in Linux 5.16,
      which has been proved to benefit the scheduling performance (e.g.
      load balance and wake_affine strategy) on both x86_64 and AArch64.
      
      So now in Linux 5.16 we have four-level arch-neutral CPU topology
      definition like below and a new scheduler level for clusters.
      struct cpu_topology {
          int thread_id;
          int core_id;
          int cluster_id;
          int package_id;
          int llc_id;
          cpumask_t thread_sibling;
          cpumask_t core_sibling;
          cpumask_t cluster_sibling;
          cpumask_t llc_sibling;
      }
      
      A cluster generally means a group of CPU cores which share L2 cache
      or other mid-level resources, and it is the shared resources that
      is used to improve scheduler's behavior. From the point of view of
      the size range, it's between CPU die and CPU core. For example, on
      some ARM64 Kunpeng servers, we have 6 clusters in each NUMA node,
      and 4 CPU cores in each cluster. The 4 CPU cores share a separate
      L2 cache and a L3 cache tag, which brings cache affinity advantage.
      
      In virtualization, on the Hosts which have pClusters (physical
      clusters), if we can design a vCPU topology with cluster level for
      guest kernel and have a dedicated vCPU pinning. A Cluster-Aware
      Guest kernel can also make use of the cache affinity of CPU clusters
      to gain similar scheduling performance.
      
      This patch adds infrastructure for CPU cluster level topology
      configuration and parsing, so that the user can specify cluster
      parameter if their machines support it.
      
      Signed-off-by: default avatarYanan Wang <wangyanan55@huawei.com>
      Message-Id: <20211228092221.21068-3-wangyanan55@huawei.com>
      Reviewed-by: default avatarPhilippe Mathieu-Daudé <philmd@redhat.com>
      [PMD: Added '(since 7.0)' to @clusters in qapi/machine.json]
      Signed-off-by: default avatarPhilippe Mathieu-Daudé <philmd@redhat.com>
      864c3b5c
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