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  1. Jul 26, 2022
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  10. Jun 15, 2022
    • Jagannathan Raman's avatar
      vfio-user: build library · 55116968
      Jagannathan Raman authored
      
      add the libvfio-user library as a submodule. build it as a meson
      subproject.
      
      libvfio-user is distributed with BSD 3-Clause license and
      json-c with MIT (Expat) license
      
      Signed-off-by: default avatarElena Ufimtseva <elena.ufimtseva@oracle.com>
      Signed-off-by: default avatarJohn G Johnson <john.g.johnson@oracle.com>
      Signed-off-by: default avatarJagannathan Raman <jag.raman@oracle.com>
      Reviewed-by: default avatarStefan Hajnoczi <stefanha@redhat.com>
      Message-id: c2adec87958b081d1dc8775d4aa05c897912f025.1655151679.git.jag.raman@oracle.com
      
      [Changed submodule URL to QEMU's libvfio-user mirror on GitLab. The QEMU
      project mirrors its dependencies so that it can provide full source code
      even in the event that its dependencies become unavailable. Note that
      the mirror repo is manually updated, so please contact me to make newer
      libvfio-user commits available. If I become a bottleneck we can set up a
      cronjob.
      
      Updated scripts/meson-buildoptions.sh to match the meson_options.txt
      change. Failure to do so can result in scripts/meson-buildoptions.sh
      being modified by the build system later on and you end up with a dirty
      working tree.
      --Stefan]
      
      Signed-off-by: default avatarStefan Hajnoczi <stefanha@redhat.com>
      55116968
  11. Jun 14, 2022
  12. Jun 06, 2022
  13. Jun 01, 2022
  14. May 18, 2022
  15. May 17, 2022
  16. May 16, 2022
  17. May 13, 2022
    • Ben Widawsky's avatar
      hw/pxb: Allow creation of a CXL PXB (host bridge) · 4f8db871
      Ben Widawsky authored
      
      This works like adding a typical pxb device, except the name is
      'pxb-cxl' instead of 'pxb-pcie'. An example command line would be as
      follows:
        -device pxb-cxl,id=cxl.0,bus="pcie.0",bus_nr=1
      
      A CXL PXB is backward compatible with PCIe. What this means in practice
      is that an operating system that is unaware of CXL should still be able
      to enumerate this topology as if it were PCIe.
      
      One can create multiple CXL PXB host bridges, but a host bridge can only
      be connected to the main root bus. Host bridges cannot appear elsewhere
      in the topology.
      
      Note that as of this patch, the ACPI tables needed for the host bridge
      (specifically, an ACPI object in _SB named ACPI0016 and the CEDT) aren't
      created. So while this patch internally creates it, it cannot be
      properly used by an operating system or other system software.
      
      Also necessary is to add an exception to scripts/device-crash-test
      similar to that for exiting pxb as both must created on a PCIexpress
      host bus.
      
      Signed-off-by: default avatarBen Widawsky <ben.widawsky@intel.com>
      Signed-off-by: default avatarJonathan.Cameron <Jonathan.Cameron@huawei.com>
      Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
      Message-Id: <20220429144110.25167-15-Jonathan.Cameron@huawei.com>
      Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      4f8db871
  18. May 12, 2022
  19. May 09, 2022
  20. May 07, 2022
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