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  1. Sep 16, 2020
  2. Sep 15, 2020
  3. Sep 14, 2020
    • Peter Maydell's avatar
      Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200914-1' into staging · 2d2c73d0
      Peter Maydell authored
      
       * hw/misc/a9scu: Do not allow invalid CPU count
       * hw/misc/a9scu: Minor cleanups
       * hw/timer/armv7m_systick: assert that board code set system_clock_scale
       * decodetree: Improve identifier matching
       * target/arm: Clean up neon fp insn size field decode
       * target/arm: Remove KVM support for 32-bit Arm hosts
       * hw/arm/mps2: New board models mps2-an386, mps2-an500
       * Deprecate Unicore32 port
       * Deprecate lm32 port
       * target/arm: Count PMU events when MDCR.SPME is set
       * hw/arm: versal-virt: Correct the tx/rx GEM clocks
       * New Nuvoton iBMC board models npcm750-evb, quanta-gsj
      
      # gpg: Signature made Mon 14 Sep 2020 16:02:06 BST
      # gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
      # gpg:                issuer "peter.maydell@linaro.org"
      # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
      # gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
      # gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
      # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE
      
      * remotes/pmaydell/tags/pull-target-arm-20200914-1: (32 commits)
        tests/acceptance: console boot tests for quanta-gsj
        docs/system: Add Nuvoton machine documentation
        hw/arm/npcm7xx: add board setup stub for CPU and UART clocks
        hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj
        hw/ssi: NPCM7xx Flash Interface Unit device model
        hw/mem: Stubbed out NPCM7xx Memory Controller model
        hw/nvram: NPCM7xx OTP device model
        hw/arm: Load -bios image as a boot ROM for npcm7xx
        roms: Add virtual Boot ROM for NPCM7xx SoCs
        hw/arm: Add two NPCM7xx-based machines
        hw/arm: Add NPCM730 and NPCM750 SoC models
        hw/timer: Add NPCM7xx Timer device model
        hw/misc: Add NPCM7xx Clock Controller device model
        hw/misc: Add NPCM7xx System Global Control Registers device model
        hw/arm: versal-virt: Correct the tx/rx GEM clocks
        target/arm: Count PMU events when MDCR.SPME is set
        Deprecate lm32 port
        Deprecate Unicore32 port
        docs/system/arm/mps2.rst: Make board list consistent
        hw/arm/mps2: New board model mps2-an500
        ...
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      2d2c73d0
    • Havard Skinnemoen's avatar
      tests/acceptance: console boot tests for quanta-gsj · 4fe986dd
      Havard Skinnemoen authored
      
      This adds two acceptance tests for the quanta-gsj machine.
      
      One test downloads a lightly patched openbmc flash image from github and
      verifies that it boots all the way to the login prompt.
      
      The other test downloads a kernel, initrd and dtb built from the same
      openbmc source and verifies that the kernel detects all CPUs and boots
      to the point where it can't find the root filesystem (because we have no
      flash image in this case).
      
      Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
      Tested-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
      Signed-off-by: default avatarHavard Skinnemoen <hskinnemoen@google.com>
      Message-id: 20200911052101.2602693-15-hskinnemoen@google.com
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      4fe986dd
    • Havard Skinnemoen's avatar
      docs/system: Add Nuvoton machine documentation · 82c703fe
      Havard Skinnemoen authored
      
      Reviewed-by: default avatarCédric Le Goater <clg@kaod.org>
      Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
      Signed-off-by: default avatarHavard Skinnemoen <hskinnemoen@google.com>
      Message-id: 20200911052101.2602693-14-hskinnemoen@google.com
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      82c703fe
    • Havard Skinnemoen's avatar
      hw/arm/npcm7xx: add board setup stub for CPU and UART clocks · 2ddae9cc
      Havard Skinnemoen authored
      
      When booting directly into a kernel, bypassing the boot loader, the CPU and
      UART clocks are not set up correctly. This makes the system appear very
      slow, and causes the initrd boot test to fail when optimization is off.
      
      The UART clock must run at 24 MHz. The default 25 MHz reference clock
      cannot achieve this, so switch to PLL2/2 @ 480 MHz, which works
      perfectly with the default /20 divider.
      
      The CPU clock should run at 800 MHz, so switch it to PLL1/2. PLL1 runs
      at 800 MHz by default, so we need to double the feedback divider as well
      to make it run at 1600 MHz (so PLL1/2 runs at 800 MHz).
      
      We don't bother checking for PLL lock because we know our emulated PLLs
      lock instantly.
      
      Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
      Tested-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
      Signed-off-by: default avatarHavard Skinnemoen <hskinnemoen@google.com>
      Message-id: 20200911052101.2602693-13-hskinnemoen@google.com
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      2ddae9cc
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