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  1. Jan 11, 2022
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  7. Jan 08, 2022
    • Richard Henderson's avatar
      Merge tag 'bsd-user-arm-pull-request' of gitlab.com:bsdimp/qemu into staging · df722e33
      Richard Henderson authored 
      bsd-user: arm (32-bit) support

This series of patches brings in 32-bit arm support for bsd-user.  It implements
all the bits needed to do image activation, signal handling, stack management
and threading. This allows us to get to the "Hello World" level. The arm and x86
code are now the same as in the bsd-user fork. For full context, the fork is at
https://github.com/qemu-bsd-user/qemu-bsd-user/tree/blitz

 (though the the recent
sig{bus,segv} needed updates are incomplete).

v5 changes:
   o Moved to using the CPUArchState typedef and move
     set_sigtramp_args, get_mcontext, set_mcontext, and
     get_ucontext_sigreturn prototypes to
     bsd-user/freebsd/target_os_ucontext.h
   o Fix issues with arm's set_mcontext related to masking
     and remove an unnecessary check.

We're down to only one hunk needing review:
    bsd-user/arm/target_arch_signal.c: arm set_mcontext

Warnings that should be ignored:
   o make checkpatch has a couple of complaints about the comments for the
     signal trampoline, since it's a false positive IMHO.
WARNING: Block comments use a leading /* on a separate line
+    /* 8 */ sys_sigreturn,
WARNING: Block comments use a leading /* on a separate line
+    /* 9 */ sys_exit

# gpg: Signature made Fri 07 Jan 2022 11:36:37 PM PST
# gpg:                using RSA key 2035F894B00AA3CF7CCDE1B76C1CD1287DB01100
# gpg: Good signature from "Warner Losh <wlosh@netflix.com>" [unknown]
# gpg:                 aka "Warner Losh <imp@bsdimp.com>" [unknown]
# gpg:                 aka "Warner Losh <imp@freebsd.org>" [unknown]
# gpg:                 aka "Warner Losh <imp@village.org>" [unknown]
# gpg:                 aka "Warner Losh <wlosh@bsdimp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 2035 F894 B00A A3CF 7CCD  E1B7 6C1C D128 7DB0 1100

* tag 'bsd-user-arm-pull-request' of gitlab.com:bsdimp/qemu: (37 commits)
  bsd-user: add arm target build
  bsd-user/freebsd/target_os_ucontext.h: Require TARGET_*CONTEXT_SIZE
  bsd-user/arm/signal.c: arm get_ucontext_sigreturn
  bsd-user/arm/signal.c: arm set_mcontext
  bsd-user/arm/signal.c: arm get_mcontext
  bsd-user/arm/signal.c: arm set_sigtramp_args
  bsd-user/arm/target_arch_signal.h: Define size of *context_t
  bsd-user/arm/target_arch_signal.h: arm machine context and trapframe for signals
  bsd-user/arm/target_arch_signal.h: arm specific signal registers and stack
  bsd-user/arm/target_arch_elf.h: arm get_hwcap2 impl
  bsd-user/arm/target_arch_elf.h: arm get hwcap
  bsd-user/arm/target_arch_elf.h: arm defines for ELF
  bsd-user/arm/target_arch_thread.h: Routines to create and switch to a thread
  bsd-user/arm/target_arch_sigtramp.h: Signal Trampoline for arm
  bsd-user/arm/target_arch_vmparam.h: Parameters for arm address space
  bsd-user/arm/target_arch_reg.h: Implement core dump register copying
  bsd-user/arm/target_arch_cpu.h: Implement system call dispatch
  bsd-user/arm/target_arch_cpu.h: Implement data abort exceptions
  bsd-user/arm/target_arch_cpu.h: Implement trivial EXCP exceptions
  bsd-user/arm/target_arch_cpu.h: Dummy target_cpu_loop implementation
  ...

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      df722e33
    • Richard Henderson's avatar
      Merge tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu into staging · afe33262
      Richard Henderson authored 
      
Second RISC-V PR for QEMU 7.0

 - Fix illegal instruction when PMP is disabled
 - SiFive PDMA 64-bit support
 - SiFive PLIC cleanups
 - Mark Hypervisor extension as non experimental
 - Enable Hypervisor extension by default
 - Support 32 cores on the virt machine
 - Corrections for the Vector extension
 - Experimental support for 128-bit CPUs
 - stval and mtval support for illegal instructions

# gpg: Signature made Fri 07 Jan 2022 09:50:11 PM PST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu: (37 commits)
  target/riscv: Implement the stval/mtval illegal instruction
  target/riscv: Fixup setting GVA
  target/riscv: Set the opcode in DisasContext
  target/riscv: actual functions to realize crs 128-bit insns
  target/riscv: modification of the trans_csrxx for 128-bit support
  target/riscv: helper functions to wrap calls to 128-bit csr insns
  target/riscv: adding high part of some csrs
  target/riscv: support for 128-bit M extension
  target/riscv: support for 128-bit arithmetic instructions
  target/riscv: support for 128-bit shift instructions
  target/riscv: support for 128-bit U-type instructions
  target/riscv: support for 128-bit bitwise instructions
  target/riscv: accessors to registers upper part and 128-bit load/store
  target/riscv: moving some insns close to similar insns
  target/riscv: setup everything for rv64 to support rv128 execution
  target/riscv: array for the 64 upper bits of 128-bit registers
  target/riscv: separation of bitwise logic and arithmetic helpers
  target/riscv: additional macros to check instruction support
  qemu/int128: addition of div/rem 128-bit operations
  exec/memop: Adding signed quad and octo defines
  ...

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      afe33262
    • Warner Losh's avatar
      bsd-user: add arm target build · 18fe5d99
      Warner Losh authored 
      
CC: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: default avatarWarner Losh <imp@bsdimp.com>
Acked-by: default avatarKyle Evans <kevans@FreeBSD.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      18fe5d99
    • Warner Losh's avatar
      bsd-user/freebsd/target_os_ucontext.h: Require TARGET_*CONTEXT_SIZE · ca4fc704
      Warner Losh authored 
      
Now that all architecutres define TARGET_[MU]CONTEXT_SIZE, enforce
requiring them and always check the sizeof target_{u,m}context_t
sizes.

Signed-off-by: default avatarWarner Losh <imp@bsdimp.com>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      ca4fc704
    • Warner Losh's avatar
      bsd-user/arm/signal.c: arm get_ucontext_sigreturn · 3ac34cc9
      Warner Losh authored 
      
Update ucontext to implement sigreturn.

Signed-off-by: default avatarStacey Son <sson@FreeBSD.org>
Signed-off-by: default avatarWarner Losh <imp@bsdimp.com>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      3ac34cc9