- Apr 20, 2022
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Richard Henderson authored
Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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- Apr 19, 2022
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Peter Maydell authored
Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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- Apr 12, 2022
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Peter Maydell authored
Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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- Apr 08, 2022
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Wentao Liang authored
A potential Use-after-free was reported in virtio_iommu_handle_command when using virtio-iommu: > I find a potential Use-after-free in QEMU 6.2.0, which is in > virtio_iommu_handle_command() (./hw/virtio/virtio-iommu.c). > > > Specifically, in the loop body, the variable 'buf' allocated at line 639 can be > freed by g_free() at line 659. However, if the execution path enters the loop > body again and the if branch takes true at line 616, the control will directly > jump to 'out' at line 651. At this time, 'buf' is a freed pointer, which is not > assigned with an allocated memory but used at line 653. As a result, a UAF bug > is triggered. > > > > 599 for (;;) { > ... > 615 sz = iov_to_buf(iov, iov_cnt, 0, &head, sizeof(head)); > 616 if (unlikely(sz != sizeof(head))) { > 617 tail.status = VIRTIO_IOMMU_S_DEVERR; > 618 goto out; > 619 } > ... > 639 buf = g_malloc0(output_size); > ... > 651 out: > 652 sz = iov_from_buf(elem->in_sg, elem->in_num, 0, > 653 buf ? buf : &tail, output_size); > ... > 659 g_free(buf); > > We can fix it by set ‘buf‘ to NULL after freeing it: > > > 651 out: > 652 sz = iov_from_buf(elem->in_sg, elem->in_num, 0, > 653 buf ? buf : &tail, output_size); > ... > 659 g_free(buf); > +++ buf = NULL; > 660 } Fix as suggested by the reporter. Signed-off-by:
Wentao Liang <Wentao_Liang_g@163.com> Signed-off-by:
Michael S. Tsirkin <mst@redhat.com> Message-id: 20220407095047.50371-1-mst@redhat.com Message-ID: <20220406040445-mutt-send-email-mst@kernel.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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git://git.kraxel.org/qemuPeter Maydell authored
two cursor/qxl related security fixes. # gpg: Signature made Fri 08 Apr 2022 05:37:16 BST # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * tag 'fixes-20220408-pull-request' of git://git.kraxel.org/qemu : ui/cursor: fix integer overflow in cursor_alloc (CVE-2021-4206) display/qxl-render: fix race condition in qxl_cursor (CVE-2021-4207) Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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- Apr 07, 2022
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Mauro Matteo Cascella authored
Prevent potential integer overflow by limiting 'width' and 'height' to 512x512. Also change 'datasize' type to size_t. Refer to security advisory https://starlabs.sg/advisories/22-4206/ for more information. Fixes: CVE-2021-4206 Signed-off-by:
Mauro Matteo Cascella <mcascell@redhat.com> Reviewed-by:
Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220407081712.345609-1-mcascell@redhat.com> Signed-off-by:
Gerd Hoffmann <kraxel@redhat.com>
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Mauro Matteo Cascella authored
Avoid fetching 'width' and 'height' a second time to prevent possible race condition. Refer to security advisory https://starlabs.sg/advisories/22-4207/ for more information. Fixes: CVE-2021-4207 Signed-off-by:
Mauro Matteo Cascella <mcascell@redhat.com> Reviewed-by:
Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220407081106.343235-1-mcascell@redhat.com> Signed-off-by:
Gerd Hoffmann <kraxel@redhat.com>
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- Apr 06, 2022
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Peter Maydell authored
Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Dr. David Alan Gilbert authored
vmstate_acpi_pcihp_use_acpi_index() was expecting AcpiPciHpState as state but it actually received PIIX4PMState, because VMSTATE_PCI_HOTPLUG is a macro and not another struct. So it ended up accessing random pointer, which resulted in 'false' return value and acpi_index field wasn't ever sent. However in 7.0 that pointer de-references to value > 0, and destination QEMU starts to expect the field which isn't sent in migratioon stream from older QEMU (6.2 and older). As result migration fails with: qemu-system-x86_64: Missing section footer for 0000:00:01.3/piix4_pm qemu-system-x86_64: load of migration failed: Invalid argument In addition with QEMU-6.2, destination due to not expected state, also never expects the acpi_index field in migration stream. Q35 is not affected as it always sends/expects the field as long as acpi based PCI hotplug is enabled. Fix issue by introducing compat knob to never send/expect acpi_index in migration stream for 6.2 and older PC machine types and always send it for 7.0 and newer PC machine types. Diagnosed-by:
Dr. David Alan Gilbert <dgilbert@redhat.com> Fixes: b32bd763 ("pci: introduce acpi-index property for PCI device") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/932 Signed-off-by:
Igor Mammedov <imammedo@redhat.com> Reviewed-by:
Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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- Apr 05, 2022
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https://gitlab.com/bonzini/qemuPeter Maydell authored
* fix vss-win32 compilation with clang++ * update Coverity model * add measurement calculation to amd-memory-encryption docs # gpg: Signature made Tue 05 Apr 2022 09:42:59 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu : docs/system/i386: Add measurement calculation details to amd-memory-encryption qga/vss-win32: fix compilation with clang++ coverity: update model for latest tools Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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git://repo.or.cz/qemu/armbruPeter Maydell authored
QAPI patches patches for 2022-04-05 # gpg: Signature made Tue 05 Apr 2022 11:32:05 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * tag 'pull-qapi-2022-04-05' of git://repo.or.cz/qemu/armbru : qapi: Fix calc-dirty-rate example qapi: fix example of query-memdev command qapi: fix example of query-cpus-fast command qapi: fix example of trace-event-get-state command qapi: fix example of query-colo-status command qapi: fix example of query-vnc command qapi: fix example of query-spice command qapi: fix example of query-named-block-nodes command qapi: fix examples: replay-break and replay-seek qapi: fix example of netdev_add command Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Peter Maydell authored
Merge tag 'pull-target-arm-20220405' of https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * docs/system/devices/can.rst: correct links to CTU CAN FD IP core documentation. * xlnx-bbram: hw/nvram: Fix uninitialized Error * # gpg: Signature made Tue 05 Apr 2022 10:26:21 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20220405' of https://git.linaro.org/people/pmaydell/qemu-arm : docs/system/devices/can.rst: correct links to CTU CAN FD IP core documentation. xlnx-bbram: hw/nvram: Fix uninitialized Error * Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Markus Armbruster authored
The example shows {"command": ...}, which is wrong. Fix it to {"execute": ...}. Signed-off-by:
Markus Armbruster <armbru@redhat.com> Message-Id: <20220401082028.3583296-1-armbru@redhat.com> Reviewed-by:
Victor Toso <victortoso@redhat.com>
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Victor Toso authored
Example output is missing mandatory argument @share for the return JSON object. Add it. Signed-off-by:
Victor Toso <victortoso@redhat.com> Message-Id: <20220331190633.121077-10-victortoso@redhat.com> Reviewed-by:
Markus Armbruster <armbru@redhat.com> Signed-off-by:
Markus Armbruster <armbru@redhat.com>
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Victor Toso authored
Example output contains member @arch that was removed in 445a5b40 "machine: remove 'arch' field from 'query-cpus-fast' QMP command". Fix it. Signed-off-by:
Victor Toso <victortoso@redhat.com> Message-Id: <20220331190633.121077-9-victortoso@redhat.com> Reviewed-by:
Markus Armbruster <armbru@redhat.com> Signed-off-by:
Markus Armbruster <armbru@redhat.com>
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Victor Toso authored
The example output is missing the mandatory member @vcpu. Fix it. Signed-off-by:
Victor Toso <victortoso@redhat.com> Message-Id: <20220331190633.121077-8-victortoso@redhat.com> Reviewed-by:
Markus Armbruster <armbru@redhat.com> Signed-off-by:
Markus Armbruster <armbru@redhat.com>
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Victor Toso authored
The example output is missing the mandatory member @last-mode in the return value. Fix it. Signed-off-by:
Victor Toso <victortoso@redhat.com> Message-Id: <20220331190633.121077-7-victortoso@redhat.com> Reviewed-by:
Markus Armbruster <armbru@redhat.com> Signed-off-by:
Markus Armbruster <armbru@redhat.com>
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Victor Toso authored
The return value is missing the mandatory member @websocket. Fix it. Signed-off-by:
Victor Toso <victortoso@redhat.com> Message-Id: <20220331190633.121077-6-victortoso@redhat.com> Reviewed-by:
Markus Armbruster <armbru@redhat.com> Signed-off-by:
Markus Armbruster <armbru@redhat.com>
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Victor Toso authored
Example output is missing mandatory members @migrated and @mouse-mode. Fix it. Signed-off-by:
Victor Toso <victortoso@redhat.com> Message-Id: <20220331190633.121077-5-victortoso@redhat.com> Reviewed-by:
Markus Armbruster <armbru@redhat.com> Signed-off-by:
Markus Armbruster <armbru@redhat.com>
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Victor Toso authored
Example output is missing mandatory member @detect_zeroes. Fix it. Signed-off-by:
Victor Toso <victortoso@redhat.com> Message-Id: <20220331190633.121077-4-victortoso@redhat.com> Reviewed-by:
Markus Armbruster <armbru@redhat.com> Signed-off-by:
Markus Armbruster <armbru@redhat.com>
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Victor Toso authored
Both examples outputs are using @data member for the arguments. This is wrong. The expected member for the QMP is @arguments. Fix it. Signed-off-by:
Victor Toso <victortoso@redhat.com> Message-Id: <20220331190633.121077-3-victortoso@redhat.com> Reviewed-by:
Markus Armbruster <armbru@redhat.com> Signed-off-by:
Markus Armbruster <armbru@redhat.com>
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Victor Toso authored
Example output has the optional member @dnssearch as string type. It should be an array of String objects instead. Fix it. For reference, see NetdevUserOptions. Signed-off-by:
Victor Toso <victortoso@redhat.com> Message-Id: <20220401110712.26911-1-victortoso@redhat.com> Reviewed-by:
Markus Armbruster <armbru@redhat.com> [Commit message tweaked for precision] Signed-off-by:
Markus Armbruster <armbru@redhat.com>
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Dov Murik authored
Add a section explaining how the Guest Owner should calculate the expected guest launch measurement for SEV and SEV-ES. Also update the name and links to the SEV API Spec document. Signed-off-by:
Dov Murik <dovmurik@linux.ibm.com> Suggested-by:
Daniel P. Berrangé <berrange@redhat.com> Reviewed-by:
Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20220217110059.2320497-1-dovmurik@linux.ibm.com> Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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Helge Konetzka authored
This fixes: qga/vss-win32/install.cpp:49:24: error: cannot initialize a variable of type 'char *' with an rvalue of type 'const char *' char *msg = NULL, *nul = strchr(text, '('); ^ ~~~~~~~~~~~~~~~~~ Signed-off-by:
Helge Konetzka <hk@zapateado.de> Reviewed-by:
Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Konstantin Kostiuk <kkostiuk@redhat.com> Message-Id: <39400817-3dc9-516d-9096-bc1f68862531@zapateado.de> Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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Paolo Bonzini authored
Coverity is now rejecting incomplete types in the modeling file. Just use a random number (in the neighborhood of the actual one) for the size of a GIOChannel. Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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Pavel Pisa authored
Signed-off-by:
Pavel Pisa <pisa@cmp.felk.cvut.cz> Reviewed-by:
Francisco Iglesias <frasse.iglesias@gmail.com> Message-id: 20220402204523.32643-1-pisa@cmp.felk.cvut.cz Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Tong Ho authored
This adds required initialization of Error * variable. Signed-off-by:
Tong Ho <tong.ho@xilinx.com> Reviewed-by:
Francisco Iglesias <frasse.iglesias@gmail.com> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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- Apr 04, 2022
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https://github.com/legoater/qemuPeter Maydell authored
ppc-7.0 queue: * Coverity fixes * Fix for a memory leak issue # gpg: Signature made Mon 04 Apr 2022 09:45:51 BST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-ppc-20220404' of https://github.com/legoater/qemu : linux-user/ppc: Narrow type of ccr in save_user_regs ppc/pnv: Fix number of registers in the PCIe controller on POWER9 hw/ppc: free env->tb_env in spapr_unrealize_vcpu() Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored
Coverity warns that we shift a 32-bit value by N, and then accumulate it into a 64-bit type (target_ulong on ppc64). The ccr is always 8 * 4-bit fields, and thus is always a 32-bit quantity; narrow the type to avoid the warning. Fixes: Coverity CID 1487223 Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Reviewed-by:
Cédric Le Goater <clg@kaod.org> Message-Id: <20220401191643.330393-1-richard.henderson@linaro.org> Signed-off-by:
Cédric Le Goater <clg@kaod.org>
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Frederic Barrat authored
The spec defines 3 registers, even though only index 0 and 2 are valid on POWER9. The same model is used on POWER10. Register 1 is defined there but we currently don't use it in skiboot. So we can keep reporting an error on write. Reported by Coverity (CID 1487176). Fixes: 4f9924c4 ("ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge") Suggested-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by:
Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220401091925.770803-1-fbarrat@linux.ibm.com> Signed-off-by:
Cédric Le Goater <clg@kaod.org>
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Daniel Henrique Barboza authored
The timebase is allocated during spapr_realize_vcpu() and it's not freed. This results in memory leaks when doing vcpu unplugs: ==636935== ==636935== 144 (96 direct, 48 indirect) bytes in 1 blocks are definitely lost in loss record 6 ,461 of 8,135 ==636935== at 0x4897468: calloc (vg_replace_malloc.c:760) ==636935== by 0x5077213: g_malloc0 (in /usr/lib64/libglib-2.0.so.0.6400.4) ==636935== by 0x507757F: g_malloc0_n (in /usr/lib64/libglib-2.0.so.0.6400.4) ==636935== by 0x93C3FB: cpu_ppc_tb_init (ppc.c:1066) ==636935== by 0x97BC2B: spapr_realize_vcpu (spapr_cpu_core.c:268) ==636935== by 0x97C01F: spapr_cpu_core_realize (spapr_cpu_core.c:337) ==636935== by 0xD4626F: device_set_realized (qdev.c:531) ==636935== by 0xD55273: property_set_bool (object.c:2273) ==636935== by 0xD523DF: object_property_set (object.c:1408) ==636935== by 0xD588B7: object_property_set_qobject (qom-qobject.c:28) ==636935== by 0xD52897: object_property_set_bool (object.c:1477) ==636935== by 0xD4579B: qdev_realize (qdev.c:333) ==636935== This patch adds a cpu_ppc_tb_free() helper in hw/ppc/ppc.c to allow us to free the timebase. This leak is then solved by calling cpu_ppc_tb_free() in spapr_unrealize_vcpu(). Fixes: 6f4b5c3e ("spapr: CPU hot unplug support") Signed-off-by:
Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by:
Cédric Le Goater <clg@kaod.org> Reviewed-by:
David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220329124545.529145-2-danielhb413@gmail.com> Signed-off-by:
Cédric Le Goater <clg@kaod.org>
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- Apr 02, 2022
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https://gitlab.com/thuth/qemuPeter Maydell authored
* Fix some compilation issues * Fix overflow calculation in s390x emulation * Update location of lockdown.yml in MAINTAINERS file # gpg: Signature made Fri 01 Apr 2022 12:27:38 BST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2022-04-01' of https://gitlab.com/thuth/qemu : trace: fix compilation with lttng-ust >= 2.13 9p: move P9_XATTR_SIZE_MAX from 9p.h to 9p.c meson.build: Fix dependency of page-vary-common.c to config-poison.h target/s390x: Fix determination of overflow condition code after subtraction target/s390x: Fix determination of overflow condition code after addition misc: Fixes MAINTAINERS's path .github/workflows/lockdown.yml Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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- Apr 01, 2022
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Peter Maydell authored
Merge tag 'pull-target-arm-20220401' of https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * target/arm: Fix some bugs in secure EL2 handling * target/arm: Fix assert when !HAVE_CMPXCHG128 * MAINTAINERS: change Fred Konrad's email address # gpg: Signature made Fri 01 Apr 2022 15:59:59 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20220401' of https://git.linaro.org/people/pmaydell/qemu-arm : target/arm: Don't use DISAS_NORETURN in STXP !HAVE_CMPXCHG128 codegen MAINTAINERS: change Fred Konrad's email address target/arm: Determine final stage 2 output PA space based on original IPA target/arm: Take VSTCR.SW, VTCR.NSW into account in final stage 2 walk target/arm: Check VSTCR.SW when assigning the stage 2 output PA space target/arm: Fix MTE access checks for disabled SEL2 Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Peter Maydell authored
Sixth RISC-V PR for QEMU 7.0 This is a last minute RISC-V PR for 7.0. It includes a fix to avoid leaking no translation TLB entries. This incorrectly cached uncachable baremetal entries. This would break Linux boot while single stepping. As the fix is pretty straight forward (flush the cache more often) it's being pulled in for 7.0. At the same time I have included a RISC-V vector extension fixup patch. # gpg: Signature made Fri 01 Apr 2022 00:33:58 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * tag 'pull-riscv-to-apply-20220401' of github.com:alistair23/qemu: target/riscv: rvv: Add missing early exit condition for whole register load/store target/riscv: Avoid leaking "no translation" TLB entries Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Peter Maydell authored
In gen_store_exclusive(), if the host does not have a cmpxchg128 primitive then we generate bad code for STXP for storing two 64-bit values. We generate a call to the exit_atomic helper, which never returns, and set is_jmp to DISAS_NORETURN. However, this is forgetting that we have already emitted a brcond that jumps over this call for the case where we don't hold the exclusive. The effect is that we don't generate any code to end the TB for the exclusive-not-held execution path, which falls into the "exit with TB_EXIT_REQUESTED" code that gen_tb_end() emits. This then causes an assert at runtime when cpu_loop_exec_tb() sees an EXIT_REQUESTED TB return that wasn't for an interrupt or icount. In particular, you can hit this case when using the clang sanitizers and trying to run the xlnx-versal-virt acceptance test in 'make check-acceptance'. This bug was masked until commit 848126d1 ("meson: move int128 checks from configure") because we used to set CONFIG_CMPXCHG128=1 and avoid the buggy codepath, but after that we do not. Fix the bug by not setting is_jmp. The code after the exit_atomic call up to the fail_label is dead, but TCG is smart enough to eliminate it. We do need to set 'tmp' to some valid value, though (in the same way the exit_atomic-using code in tcg/tcg-op.c does). Resolves: https://gitlab.com/qemu-project/qemu/-/issues/953 Signed-off-by:
Peter Maydell <peter.maydell@linaro.org> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20220331150858.96348-1-peter.maydell@linaro.org
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Frederic Konrad authored
frederic.konrad@adacore.com and konrad@adacore.com will stop working starting 2022-04-01. Use my personal email instead. Signed-off-by:
Frederic Konrad <frederic.konrad@adacore.com> Reviewed-by:
Fabien Chouteau <chouteau@adacore.com <clg@kaod.org>> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1648643217-15811-1-git-send-email-frederic.konrad@adacore.com Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Idan Horowitz authored
As per the AArch64.S2Walk() pseudo-code in the ARMv8 ARM, the final decision as to the output address's PA space based on the SA/SW/NSA/NSW bits needs to take the input IPA's PA space into account, and not the PA space of the result of the stage 2 walk itself. Signed-off-by:
Idan Horowitz <idan.horowitz@gmail.com> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20220327093427.1548629-4-idan.horowitz@gmail.com [PMM: fixed commit message typo] Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Idan Horowitz authored
As per the AArch64.SS2InitialTTWState() psuedo-code in the ARMv8 ARM the initial PA space used for stage 2 table walks is assigned based on the SW and NSW bits of the VSTCR and VTCR registers. This was already implemented for the recursive stage 2 page table walks in S1_ptw_translate(), but was missing for the final stage 2 walk. Signed-off-by:
Idan Horowitz <idan.horowitz@gmail.com> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20220327093427.1548629-3-idan.horowitz@gmail.com Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Idan Horowitz authored
As per the AArch64.SS2OutputPASpace() psuedo-code in the ARMv8 ARM when the PA space of the IPA is non secure, the output PA space is secure if and only if all of the bits VTCR.<NSW, NSA>, VSTCR.<SW, SA> are not set. Signed-off-by:
Idan Horowitz <idan.horowitz@gmail.com> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20220327093427.1548629-2-idan.horowitz@gmail.com Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Idan Horowitz authored
While not mentioned anywhere in the actual specification text, the HCR_EL2.ATA bit is treated as '1' when EL2 is disabled at the current security state. This can be observed in the psuedo-code implementation of AArch64.AllocationTagAccessIsEnabled(). Signed-off-by:
Idan Horowitz <idan.horowitz@gmail.com> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20220328173107.311267-1-idan.horowitz@gmail.com Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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