target/riscv: Add MXL/SXL/UXL to TB_FLAGS
Begin adding support for switching XLEN at runtime. Extract the effective XLEN from MISA and MSTATUS and store for use during translation. Reviewed-by:LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-6-richard.henderson@linaro.org Signed-off-by:
Alistair Francis <alistair.francis@wdc.com>
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- target/riscv/cpu.c 8 additions, 0 deletionstarget/riscv/cpu.c
- target/riscv/cpu.h 2 additions, 0 deletionstarget/riscv/cpu.h
- target/riscv/cpu_helper.c 33 additions, 0 deletionstarget/riscv/cpu_helper.c
- target/riscv/csr.c 3 additions, 0 deletionstarget/riscv/csr.c
- target/riscv/translate.c 1 addition, 1 deletiontarget/riscv/translate.c
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