target/riscv: Support mcycle/minstret write operation
mcycle/minstret are actually WARL registers and can be written with any given value. With SBI PMU extension, it will be used to store a initial value provided from supervisor OS. The Qemu also need prohibit the counter increment if mcountinhibit is set. Support mcycle/minstret through generic counter infrastructure. Reviewed-by:Alistair Francis <alistair.francis@wdc.com> Signed-off-by:
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- target/riscv/cpu.h 16 additions, 7 deletionstarget/riscv/cpu.h
- target/riscv/csr.c 112 additions, 43 deletionstarget/riscv/csr.c
- target/riscv/machine.c 23 additions, 2 deletionstarget/riscv/machine.c
- target/riscv/meson.build 2 additions, 1 deletiontarget/riscv/meson.build
- target/riscv/pmu.c 32 additions, 0 deletionstarget/riscv/pmu.c
- target/riscv/pmu.h 28 additions, 0 deletionstarget/riscv/pmu.h
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