- Feb 22, 2017
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Alessandro Di Federico authored
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Alessandro Di Federico authored
We used to provide to users the pc register, now we also provide the stack pointer register.
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- Jan 23, 2017
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Alessandro Di Federico authored
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- Jan 17, 2017
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Alessandro Di Federico authored
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- Sep 20, 2016
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Alessandro Di Federico authored
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Alessandro Di Federico authored
Do not emit the fake instruction identifying a new input instruction if we are in a MIPS delay slot.
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Alessandro Di Federico authored
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Alessandro Di Federico authored
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Alessandro Di Federico authored
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Alessandro Di Federico authored
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Alessandro Di Federico authored
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Alessandro Di Federico authored
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Alessandro Di Federico authored
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- Sep 19, 2016
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Alessandro Di Federico authored
* Always force to 0 `reserverd_va` * Some x86 initialization
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Alessandro Di Federico authored
We don't want to crash in case an unexpected instruction is translated. The appropriate solution here would be to return an error code, but the current code doesn't support that.
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Alessandro Di Federico authored
Having explicit accesses to the CPU state is currently mandatory for usage as LLVM helpers, or an abort will be emitted. This is done to ensure that we know precisely which parts of the CPU state a set of helpers access. With a more sophisticated analysis it's possible to avoid having to do this ugly hack, which make merging with upstream harder.
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Alessandro Di Federico authored
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- Mar 13, 2016
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Alessandro Di Federico authored
* Support loading of multiple libtinycodes * Implement `ptc_load` which returns an object working as the libtinycode's interface. * Various other improvements and new functions in the libtincode interface * CPU intialization * Automatically choose a CPU depending on the current architecture * Implement `initialize_cpu_state` which performs all the architecture-specific initialization steps * `mmap` memory areas before translation Feed into libtinycode the code and the corresponding address ranges, so it can mmap it and avoid translating code outside of these regions. * Implement `ptc_disassemble` * Implement some dummy functions needed by the i386 backend * Various other aesthetic changes * Make `tb_link_page` non-static * Let `ptc_instruction_*` functions take a pointer to `PTCInterface` to be able to perform sanity checks
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Alessandro Di Federico authored
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Alessandro Di Federico authored
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Alessandro Di Federico authored
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Alessandro Di Federico authored
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Alessandro Di Federico authored
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Alessandro Di Federico authored
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Alessandro Di Federico authored
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- Sep 04, 2015
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Alessandro Di Federico authored
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Alessandro Di Federico authored
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Alessandro Di Federico authored
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- Aug 26, 2015
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Alessandro Di Federico authored
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- Aug 19, 2015
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Alessandro Di Federico authored
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- Aug 16, 2015
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Alessandro Di Federico authored
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- Aug 14, 2015
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Peter Maydell authored
# gpg: Signature made Fri 14 Aug 2015 14:54:27 BST using RSA key ID C0DE3057 # gpg: Good signature from "Jeffrey Cody <jcody@redhat.com>" # gpg: aka "Jeffrey Cody <jeff@codyprime.org>" # gpg: aka "Jeffrey Cody <codyprime@gmail.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 9957 4B4D 3474 90E7 9D98 D624 BDBE 7B27 C0DE 3057 * remotes/cody/tags/block-pull-request: mirror: Fix coroutine reentrance block/mirror: limit qiov to IOV_MAX elements Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Peter Maydell authored
# gpg: Signature made Fri 14 Aug 2015 15:41:14 BST using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" * remotes/stefanha/tags/block-pull-request: throttle: add throttle_max_is_missing_limit() test throttle: refuse bps_max/iops_max without bps/iops Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Kevin Wolf authored
This fixes a regression introduced by commit dcfb3beb ("mirror: Do zero write on target if sectors not allocated"), which was reported to cause aborts with the message "Co-routine re-entered recursively". The cause for this bug is the following code in mirror_iteration_done(): if (s->common.busy) { qemu_coroutine_enter(s->common.co, NULL); } This has always been ugly because - unlike most places that reenter - it doesn't have a specific yield that it pairs with, but is more uncontrolled. What we really mean here is "reenter the coroutine if it's in one of the four explicit yields in mirror.c". This used to be equivalent with s->common.busy because neither mirror_run() nor mirror_iteration() call any function that could yield. However since commit dcfb3beb this doesn't hold true any more: bdrv_get_block_status_above() can yield. So what happens is that bdrv_get_block_status_above() wants to take a lock that is already held, so it adds itself to the queue of waiting coroutines and yields. Instead of being woken up by the unlock function, however, it gets woken up by mirror_iteration_done(), which is obviously wrong. In most cases the code actually happens to cope fairly well with such cases, but in this specific case, the unlock must already have scheduled the coroutine for wakeup when mirror_iteration_done() reentered it. And then the coroutine happened to process the scheduled restarts and tried to reenter itself recursively. This patch fixes the problem by pairing the reenter in mirror_iteration_done() with specific yields instead of abusing s->common.busy. Cc: qemu-stable@nongnu.org Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Jeff Cody <jcody@redhat.com> Message-id: 1439455310-11263-1-git-send-email-kwolf@redhat.com Signed-off-by: Jeff Cody <jcody@redhat.com>
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Jeff Cody authored
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- Aug 13, 2015
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Peter Maydell authored
MIPS patches 2015-08-13 Changes: * mips32r5-generic CPU updated and renamed to P5600 * improvements in LWL/LDL, logging and fulong2e # gpg: Signature made Thu 13 Aug 2015 17:10:59 BST using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B * remotes/lalrae/tags/mips-20150813: target-mips: Use CPU_LOG_INT for logging related to interrupts hw/pci-host/bonito: Avoid buffer overrun for bad LDMA/COP accesses target-mips: simplify LWL/LDL mask generation target-mips: update mips32r5-generic into P5600 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored
There are now no unconditional uses of qemu_log in the subdirectory. Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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Peter Maydell authored
The LDMA and COP memory regions represent four 32 bit registers each, but the memory regions themselves are 0x100 bytes large. Add guards to the read and write accessors so that bogus accesses beyond the four defined registers don't just run off the end of the bonldma and boncop structs and into whatever lies beyond. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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Aurelien Jarno authored
The LWL/LDL instructions mask the GPR with a mask depending on the address alignement. It is currently computed by doing: mask = 0x7fffffffffffffffull >> (t1 ^ 63) It's simpler to generate it by doing: mask = ~(-1 << t1) It uses one TCG instruction less, and it avoids a 32/64-bit constant loading which can take a few instructions on RISC hosts. Cc: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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Yongbok Kim authored
As full specification of P5600 is available, mips32r5-generic should be renamed to P5600 and corrected as its intention. Correct PRid and detail of configuration. Features which are not currently supported are described as FIXME. Fix Config.MM bit location Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> [leon.alrae@imgtec.com: correct cache line sizes and LLAddr shift] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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