Skip to content
Snippets Groups Projects
user avatar
Eric Auger authored
The GSIV numbers of the SPI based interrupts is not correct as
ARM_SPI_BASE was not added to the irqmap[VIRT_SMMU] value. So
this may collide with VIRTIO_MMIO irq window.

Signed-off-by: default avatarEric Auger <eric.auger@redhat.com>
Message-id: 20190312091031.5185-1-eric.auger@redhat.com
Reviewed-by: default avatarShannon Zhao <shannon.zhaosl@gmail.com>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
41c4fb94
History