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Created with Raphaël 2.2.026May2524232221191817161513121110Hexagon (tests/tcg/hexagon) Clean up Hexagon check-tcg testsconfigure: ignore --makemeson: use subproject for keycodemapdbmeson: use subproject for internal libfdtmeson: simplify logic for -Dfdtvirtio: qmp: fix memory leakslirp: update wrap to latest mastermeson: Add static glib dependency for initrd-stress.imgmeson: Remove leftover commenttarget/loongarch: Fix the vinsgr2vr/vpickve2gr instructions cause system coredumptarget/loongarch: Fix LD/ST{LE/GT} instructions get wrong CSR_ERA and CSR_BADVconfigure: unset harmful environment variablesMakefile: remove $(TESTS_PYTHON)tests/vm: fix and simplify HOST_ARCH definitiontests/docker: simplify HOST_ARCH definitionhw/scsi/lsi53c895a: Fix reentrancy issues in the LSI controller (CVE-2023-0330)lsi53c895a: disable reentrancy detection for MMIO region, toomachine: do not crash if default RAM backend name has been stolentests/qtest/ac97-test: add up-/downsampling teststests/qtest/usb-hcd-ehci-test: Check for EHCI and UHCI HCDs before using themtests/qtest/rtl8139-test: Check whether the rtl8139 device is availabletests/qtest: Check for virtio-blk before using -cdrom with the arm virt machinetests/qtest/usb-hcd-uhci-test: Check whether "usb-storage" is availablehw/mips: Use MachineClass->default_nic in the virt machinehw/arm: Use MachineClass->default_nic in the sbsa-ref machinehw/xtensa: Use MachineClass->default_nic in the virt machinehw/loongarch64: Use MachineClass->default_nic in the virt machinehw/arm: Use MachineClass->default_nic in the virt machinehw/alpha: Use MachineClass->default_nic in the alpha machinehw/hppa: Use MachineClass->default_nic in the hppa machineMerge tag 'pull-tcg-20230525' of https://gitlab.com/rth7680/qemu into stagingMerge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingtcg/riscv: Support CTZ, CLZ from Zbbtcg/riscv: Implement movcondtcg/riscv: Improve setcond expansiontcg/riscv: Support CPOP from Zbbtcg/riscv: Support REV8 from Zbbtcg/riscv: Support rotates from Zbbtcg/riscv: Use ADD.UW for guest address generationtcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb