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Created with Raphaël 2.2.07Nov6532131Oct302725232221target/riscv: Add M-mode virtual interrupt and IRQ filtering support.target/riscv: Split interrupt logic from riscv_cpu_update_mip.target/riscv: Set VS* bits to one in mideleg when H-Ext is enabledtarget/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.target/riscv: Without H-mode mask all HS mode inturrupts in mie.target/riscv: rename ext_icboz to ext_zicboztarget/riscv: rename ext_icbom to ext_zicbomtarget/riscv: rename ext_icsr to ext_zicsrtarget/riscv: rename ext_ifencei to ext_zifenceitcg/sparc64: Implement tcg_out_extrl_i64_i32tcg/optimize: Canonicalize sub2 with constants to add2tcg/optimize: Canonicalize subi to addi during optimizationtcg: Canonicalize subi to addi during opcode generationtcg/optimize: Split out arg_new_constanttcg: Eliminate duplicate env store operationstcg/optimize: Optimize env memory operationstcg/optimize: Split out cmp_better_copytcg/optimize: Pipe OptContext into reset_tstcg: Don't free vector resultstcg: Remove TCG_TARGET_HAS_neg_{i32,i64}tcg/loongarch64: Implement neg opcodestcg/mips: Implement neg opcodestcg: Remove TCG_TARGET_HAS_movcond_{i32,i64}tcg/mips: Always implement movcondtcg/mips: Split out tcg_out_setcond_inttcg: Move tcg_temp_free_* out of linetcg: Move tcg_temp_new_*, tcg_global_mem_new_* out of linetcg: Move tcg_constant_* out of linetcg: Unexport tcg_gen_op*_{i32,i64}tcg: Move tcg_gen_opN declarations to tcg-internal.htcg: Move vec_gen_* declarations to tcg-internal.htcg: Move 64-bit expanders out of linetcg: Move 32-bit expanders out of linetcg: Move generic expanders out of linetcg: Move tcg_gen_op* out of linetcg: Mark tcg_gen_op* as noinlineaccel/tcg: Fix condition for store_atom_insert_al16accel/tcg: Remove redundant case in store_atom_16host/include/loongarch64: Add atomic16 load and storetcg/loongarch64: Use cpuinfo.h