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Created with Raphaël 2.2.05May43229Apr28272625242322212019131211109654330Mar292827tcg/aarch64: Introduce HostAddresstcg/aarch64: Rationalize args to tcg_out_qemu_{ld,st}tcg/i386: Introduce tcg_out_testitcg/i386: Drop r0+r1 local variables from tcg_out_tlb_loadtcg/i386: Introduce HostAddresstcg/i386: Generalize multi-part load overlap testtcg/i386: Rationalize args to tcg_out_qemu_{ld,st}target/sparc: Remove TARGET_ALIGNED_ONLYtarget/sparc: Use cpu_ld*_code_mmutarget/sparc: Use MO_ALIGN where requiredtarget/hppa: Remove TARGET_ALIGNED_ONLYtarget/hppa: Use MO_ALIGN for system UNALIGN()target/alpha: Remove TARGET_ALIGNED_ONLYtarget/alpha: Use MO_ALIGN where requiredtarget/alpha: Use MO_ALIGN for system UNALIGN()tcg: Remove compatability helpers for qemu ld/sttarget/xtensa: Finish conversion to tcg_gen_qemu_{ld, st}_*target/sparc: Finish conversion to tcg_gen_qemu_{ld, st}_*target/s390x: Finish conversion to tcg_gen_qemu_{ld, st}_*target/mips: Finish conversion to tcg_gen_qemu_{ld,st}_*target/m68k: Finish conversion to tcg_gen_qemu_{ld,st}_*target/Hexagon: Finish conversion to tcg_gen_qemu_{ld, st}_*target/cris: Finish conversion to tcg_gen_qemu_{ld,st}_*target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_*softfloat: Fix the incorrect computation in float32_exp2hw/ppc/Kconfig: NVDIMM is a hard requirement for the pseries machinetests: tcg: ppc64: Add tests for Vector Extract Mask Instructionstcg: ppc64: Fix mask generation for vextractdmMAINTAINERS: Adding myself in the list for ppc/spaprppc: spapr: cleanup cr get/set with helpers.hw/display/sm501: Remove unneeded increment from loopaudio/pwaudio.c: Add Pipewire audio backend for QEMUMerge tag 'pull-riscv-to-apply-20230505-1' of https://github.com/alistair23/qemu into stagingtarget/riscv: add Ventana's Veyron V1 CPUriscv: Make sure an exception is raised if a pte is malformedtarget/riscv: Fix Guest Physical Address Translationtarget/riscv: Restore the predicate() NULL check behaviortarget/riscv: add TYPE_RISCV_DYNAMIC_CPUtarget/riscv: add query-cpy-definitions supporttarget/riscv: add CPU QOM header