- Sep 07, 2016
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Benjamin Herrenschmidt authored
We were one instruction off Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
Use tlb_vaddr_to_host to do a fast path single translate for the whole cache line. Also make the reservation check match the entire range. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
We don't need to call a helper for trap always and trap never which are used by Linux under some circumstances. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> -- v2. Don't generate the helper call when trapping always Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
The current alignment exception generation tries to load the opcode to put in DSISR from a context where a cpu_ldl_code() is really not a good idea. It might fault and longjmp out and that's not something we want happening here. Instead, pass the releavant opcode bits via the error_code. There are a couple of cases of alignment interrupts that won't set anything, the ones coming from access to direct store segments, but that doesn't happen in practice, nobody used direct store segments and they are gone from newer chips. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
Instead, pass GETPC() result to the corresponding helpers. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
Move the NIP update to after the conditional branch so that we don't do it if we aren't going to take the alignment exception Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
This is no longer necessary as the helpers will properly retrieve the return address when needed. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
This is no longer necessary as the helpers will properly retrieve the return address when needed. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
This is no longer necessary as the helpers will properly retrieve the return address when needed. Also remove gen_update_current_nip() which didn't seem to make much sense to me. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
This is no longer necessary as the helpers will properly retrieve the return address when needed Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
We need to pass it to the raise helper since we don't update it before the calls. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
Instead, pass GETPC() result to the corresponding helpers. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
Instead, pass GETPC() result to the corresponding helpers. This requires a bit of fiddling to get the PC (hopefully) right in the case where we generate a program check, though the hacks there are temporary, a subsequent patch will clean this all up by always having the nip already set to the right instruction when taking the fault. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> [dwg: Fix trivial checkpatch warning] Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
We don't implement imprecise FP exceptions and using store_current which sets SRR1 to the *previous* instruction never makes sense for these. So let's be truthful and make them precise, which is allowed by the architecture. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
This is no longer necessary as the helpers will properly retrieve the return address. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
Instead of relying on NIP having been updated already. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> [dwg: Fold in fix to mark function always_inline] Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
Instead of relying on NIP having been updated already Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
No other change Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
Makes things a bit more manageable Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
Makes things a bit more manageable Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
Makes things a bit more manageable Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
Makes things a bit more manageable Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
Makes things a bit more manageable Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Benjamin Herrenschmidt authored
Instead of using the same helpers called from translate.c, let's have a bunch of functions that take the various argument combinations, especially the retaddr which will be needed in subsequent patches, and leave the helpers to be just that, helpers for translate.c We don't yet convert all users, we'll go through them in subsequent patches. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> -- v2. Fix raise_exception_ra() to properly pass raddr Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Nikunj A Dadhania authored
ISA 3.0 has introduced EO - Expanded Opcode. Introduce third level indirect opcode table and corresponding parsing routines. EO (11:12) Expanded opcode field Formats: XX1 EO (11:15) Expanded opcode field Formats: VX, X, XX2 Signed-off-by:
Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> [dwg: Trivial checkpatch fixup] Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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- Sep 06, 2016
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Nikunj A Dadhania authored
maddhd: Multiply-Add High Doubleword maddhdu: Multiply-Add High Doubleword Unsigned Above two instruction are dual form and differ by 1 bit (31st bit) Multiplies two 64-bit registers (RA * RB), adds third register(RC) to the result(quadword) and returns the higher dword in the target register(RT). Signed-off-by:
Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by:
Richard Henderson <rth@twiddle.net> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Nikunj A Dadhania authored
maddld: Multiply-Add Low Doubleword Multiplies two 64-bit registers (RA * RB), adds third register(RC) to the result(quadword) and returns the lower dword in the target register(RT). Signed-off-by:
Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by:
Richard Henderson <rth@twiddle.net> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Vivek Andrew Sha authored
The CR number is provided in the opcode as - BFA (11:13) Returns: -1 if bit 0 of CR field is set 1 if bit 1 of CR field is set 0 otherwise. Signed-off-by:
Vivek Andrew Sha <vivekandrewsha@gmail.com> [ reworded commit, used 32bit ops as crf is 32bits ] Signed-off-by:
Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by:
Richard Henderson <rth@twiddle.net> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Nikunj A Dadhania authored
Search a byte in the stream of 8bytes provided in the register Suggested-by:
Richard Henderson <rth@twiddle.net> Signed-off-by:
Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by:
Richard Henderson <rth@twiddle.net> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Nikunj A Dadhania authored
Add ISA3.0: Count trailing zeros word instruction. Signed-off-by:
Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by:
Richard Henderson <rth@twiddle.net> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Sandipan Das authored
Add ISA3.0 Count trailing zeros double word Signed-off-by:
Sandipan Das <sandipandas1990@gmail.com> [ added ISA300 flag ] Signed-off-by:
Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by:
Richard Henderson <rth@twiddle.net> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Nikunj A Dadhania authored
Adding following instructions for ISA3.0 support modud: Modulo Unsigned Dword modsd: Modulo Signed Dword Signed-off-by:
Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by:
Richard Henderson <rth@twiddle.net> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Nikunj A Dadhania authored
Adding following instructions: moduw: Modulo Unsigned Word modsw: Modulo Signed Word Signed-off-by:
Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by:
Richard Henderson <rth@twiddle.net> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Nikunj A Dadhania authored
ISA 3.0 Compare Ranged Byte instruction useful for isupper/islower/isaplha kind of operation. Signed-off-by:
Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by:
Richard Henderson <rth@twiddle.net> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Nikunj A Dadhania authored
ISA 3.0 instruction for adding immediate value shifted with next instruction address and return the result in the target register. Signed-off-by:
Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by:
David Gibson <david@gibson.dropbear.id.au> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Nikunj A Dadhania authored
This flag will be used for POWER9 instructions. Signed-off-by:
Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by:
David Gibson <david@gibson.dropbear.id.au> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Aneesh Kumar K.V authored
The patch adds CPU PVR definition for POWER9 and enables QEMU to launch guests/linux-user in TCG mode. Signed-off-by:
Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> [ Added POWER9 alias, POWER9 SPAPR core and dropped MMU defines ] Signed-off-by:
Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> [dwg: Dropped sPAPR core type again for now] Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Cédric Le Goater authored
spapr_pci would also be a good candidate but the macro _FDT is slightly different. It returns and does not exit. Signed-off-by:
Cédric Le Goater <clg@kaod.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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Greg Kurz authored
We abort a few lines above if kernel_xics_fd == -1. This is only code cleanup. Signed-off-by:
Greg Kurz <groug@kaod.org> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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