Skip to content
Snippets Groups Projects
Select Git revision
  • feature/libtcg-rebase default protected
1 result
Search by author
  • Any Author
  • Anton Anton anjo
1 author
  1. Jul 10, 2020
  3. May 14, 2020
    • Peter Maydell's avatar
      target/arm: Use correct GDB XML for M-profile cores · c888f7e0
      Peter Maydell authored 
      GDB's remote protocol requires M-profile cores to use the feature
name 'org.gnu.gdb.arm.m-profile' instead of the 'org.gnu.gdb.arm.core'
feature used for A- and R-profile cores. We weren't doing this, which
meant GDB treated our M-profile cores like A-profile ones. This mostly
doesn't matter, but for instance means that it doesn't correctly
handle backtraces where an M-profile exception frame is involved.

Ship a copy of GDB's arm-m-profile.xml and use it on the M-profile
cores.  The integer registers have the same offsets as the
arm-core.xml, but register 25 is the M-profile XPSR rather than the
A-profile CPSR, so we need to update arm_cpu_gdb_read_register() and
arm_cpu_gdb_write_register() to handle XSPR reads and writes.

Fixes: https://bugs.launchpad.net/qemu/+bug/1877136


Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200507134755.13997-1-peter.maydell@linaro.org
      c888f7e0
  5. May 06, 2020
    • KONRAD Frederic's avatar
      target/m68k: fix gdb for m68xxx · a976ed3f
      KONRAD Frederic authored 
      
Currently "cf-core.xml" is sent to GDB when using any m68k flavor.  Thing is
it uses the "org.gnu.gdb.coldfire.core" feature name and gdb 8.3 then expects
a coldfire FPU instead of the default m68881 FPU.

This is not OK because the m68881 floats registers are 96 bits wide so it
crashes GDB with the following error message:

(gdb) target remote localhost:7960
Remote debugging using localhost:7960
warning: Register "fp0" has an unsupported size (96 bits)
warning: Register "fp1" has an unsupported size (96 bits)
...
Remote 'g' packet reply is too long (expected 148 bytes, got 180 bytes):    \
  00000000000[...]0000

With this patch: qemu-system-m68k -M none -cpu m68020 -s -S

(gdb) tar rem :1234
Remote debugging using :1234
warning: No executable has been specified and target does not support
determining executable automatically.  Try using the "file" command.
0x00000000 in ?? ()
(gdb) p $fp0
$1 = nan(0xffffffffffffffff)

Signed-off-by: default avatarKONRAD Frederic <frederic.konrad@adacore.com>
Signed-off-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Reviewed-by: default avatarLaurent Vivier <laurent@vivier.eu>
Message-Id: <1588094279-17913-3-git-send-email-frederic.konrad@adacore.com>
Message-Id: <20200430190122.4592-10-alex.bennee@linaro.org>
      a976ed3f
  7. Mar 19, 2020
  9. Oct 28, 2019
  11. Mar 19, 2019
  13. Feb 05, 2019
    • Doug Gale's avatar
      gdbstub: Fix i386/x86_64 machine description and add control registers · 7b0f97ba
      Doug Gale authored 
      
The machine description we send is being (silently) thrown on the floor
by GDB and GDB silently uses the default machine description, because
the xml parse fails on <feature> nested within <feature>.
Changes to the xml in qemu source code have no effect.

In addition, the default machine description has fs_base, which fails to
be retrieved, which breaks the whole register window.  Add it and the
other control registers.

Signed-off-by: default avatarDoug Gale <doug16k@gmail.com>
Message-Id: <20190124040457.2546-1-doug16k@gmail.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      7b0f97ba
  15. Jul 14, 2017
  17. Jun 21, 2017
  19. Jun 07, 2017
    • Abdallah Bouassida's avatar
      target/i386: Add GDB XML description for SSE registers · b8158192
      Abdallah Bouassida authored 
      
Add an XML description for SSE registers (XMM+MXCSR) for both X86
and X86-64 architectures in the GDB stub:
- configure: Define gdb_xml_files for the X86 targets (32 and 64bit).
- gdb-xml/i386-32bit-sse.xml & gdb-xml/i386-64bit-sse.xml: The XML files
that contain a description of the XMM + MXCSR registers.
- gdb-xml/i386-32bit.xml & gdb-xml/i386-64bit.xml: wrappers that include
the XML file of the core registers and the other XML file of the SSE registers.
- target/i386/cpu.c: Modify the gdb_core_xml_file to the new XML wrapper,
  modify the gdb_num_core_regs to fit the registers number defined in each
  XML file.

Signed-off-by: default avatarAbdallah Bouassida <abdallah.bouassida@lauterbach.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      b8158192
  21. May 05, 2017
    • Abdallah Bouassida's avatar
      target/i386: Add GDB XML register description support · 00fcd100
      Abdallah Bouassida authored 
      
This patch implements XML target description support for X86 and X86-64
architectures in the GDB stub, as the way with ARM and PowerPC:
- gdb-xml/32bit-core.xml & gdb-xml/64bit-core.xml: Adding the XML target
  description files, these files are picked from GDB source code.
- configure: Define gdb_xml_files for X86 targets.
- target/i386/cpu.c: Define gdb_core_xml_file and gdb_arch_name to add
  XML awareness for this architecture, modify the gdb_num_core_regs to
  fit the registers number defined in each XML file.

Signed-off-by: default avatarAbdallah Bouassida <abdallah.bouassida@lauterbach.com>
Message-Id: <2b3c8119-1602-28c7-eab4-296593877103@lauterbach.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      00fcd100
  23. Jan 30, 2016
  25. Oct 02, 2015
  27. Sep 07, 2015
  29. May 27, 2015
  31. Sep 01, 2014
  33. Dec 17, 2013
  35. Sep 10, 2013
  37. Jul 12, 2009
    • Nathan Froyd's avatar
      gdb-xml: fix hacks in powerpc register numbering · 22555301
      Nathan Froyd authored 
      
The powerpc xml files contained a hack--an empty, non-existent
register--for getting the register numbers to line up for
newer (XML-aware) and older (non-XML-aware) GDB.  While this hack worked
in some cases, it didn't work in all cases, notably when the user used
`finish' or `continue': GDB would attempt to read the non-existent
register and QEMU would complain.

This patch fixes things up properly.  Instead of inserting a fake
register, we explicitly declare the floating-point and SPE registers to
start at 71.  This action accomplishes the same thing as the nasty hack,
except that now GDB never tries to fetch the non-existant register 70.

Signed-off-by: default avatarNathan Froyd <froydnj@codesourcery.com>
Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      22555301
  39. Mar 07, 2009
    • Aurelien Jarno's avatar
      Work around QEMU GDB stub suboptimality · d2c75345
      Aurelien Jarno authored 
      
The current XML files claim, on floating point-supporting Power chips,
that $f0 is register 70.  This would be fine, except that register 70
for non-XML-aware GDB is FPSCR.  More importantly, 70 is less than
NUM_CORE_REGS (71) for Power, so a request for register 70 goes to the
"core" register reading routines, rather than the floating-point
register read routine we registered with gdb_register_coprocessor.

Therefore, when we are talking to an XML-aware GDB, we claim that
register has zero width, which causes the rest of QEMU's GDB stub to
send an error back to GDB, which causes GDB to be unable to read the
floating-point registers.  (The problem is also present for SPE
registers and occurs in a slightly different way for Altivec registers.)

The best way to fix this is to have the "core register" XML files for
PPC32 and PPC64 claim that there is a 4-byte register 70, which causes
$f0 to be register 71, and everything works just fine from that point
forward.

Signed-off-by: default avatarNathan Froyd <froydnj@codesourcery.com>
Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6770 c046a42c-6fe2-441c-8c8c-71466251a162
      d2c75345
  41. Mar 04, 2009
  43. Jan 24, 2009
  45. Oct 11, 2008