- Jan 04, 2021
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Huacai Chen authored
Add Loongson-3 based machine support, it use liointc as the interrupt controler and use GPEX as the pci controller. Currently it can work with both TCG and KVM. As the machine model is not based on any exiting physical hardware, the name of the machine is "loongson3-virt". It may be superseded in future by a real machine model. If this happens, then a regular deprecation procedure shall occur for "loongson3-virt" machine. We now already have a full functional Linux kernel (based on Linux-5.4.x LTS) here: https://github.com/chenhuacai/linux Of course the upstream kernel is also usable (the kvm host side and guest side have both been upstream in Linux-5.9): https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git How to use QEMU/Loongson-3? 1, Download kernel source from the above URL; 2, Build a kernel with arch/mips/configs/loongson3_defconfig; 3, Boot a Loongson-3A4000 host with this kernel (for KVM mode); 4, Build QEMU-master with this patchset; 5, modprobe kvm (only necessary for KVM mode); 6, Use QEMU with TCG: qemu-system-mips64el -M loongson3-virt,accel=tcg -cpu Loongson-3A1000 -kernel <path_to_kernel> -append ... Use QEMU with KVM: qemu-system-mips64el -M loongson3-virt,accel=kvm -cpu Loongson-3A4000 -kernel <path_to_kernel> -append ... The "-cpu" parameter is optional here and QEMU will use the correct type for TCG/KVM automatically. Co-developed-by:
Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by:
Huacai Chen <chenhuacai@kernel.org> Signed-off-by:
Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201221110538.3186646-5-chenhuacai@kernel.org> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Set TYPE_LOONGSON_MACHINE instance_size in TypeInfo, select FW_CFG_MIPS in Kconfig] Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org>
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- Nov 03, 2020
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Philippe Mathieu-Daudé authored
We deprecated the support for the 'r4k' machine for the 5.0 release (commit d32dc614), which means that our deprecation policy allows us to drop it in release 5.2. Remove the code. To repeat the rationale from the deprecation note: - this virtual machine has no specification - the Linux kernel dropped support for it 10 years ago Users are recommended to use the Malta board instead. Acked-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Thomas Huth <thuth@redhat.com> ACKed-by:
Peter Krempa <pkrempa@redhat.com> Message-Id: <20201102201311.2220005-1-f4bug@amsat.org>
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- Oct 20, 2020
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Philippe Mathieu-Daudé authored
While APEI is a generic ACPI feature (usable by X86 and ARM64), only the 'virt' machine uses it, by enabling the RAS Virtualization. See commit 2afa8c85: "hw/arm/virt: Introduce a RAS machine option"). Restrict the APEI tables generation code to the single user: the virt machine. If another machine wants to use it, it simply has to 'select ACPI_APEI' in its Kconfig. Fixes: aa16508f ("ACPI: Build related register address fields via hardware error fw_cfg blob") Acked-by:
Michael S. Tsirkin <mst@redhat.com> Reviewed-by:
Dongjiu Geng <gengdongjiu@huawei.com> Acked-by:
Laszlo Ersek <lersek@redhat.com> Reviewed-by:
Igor Mammedov <imammedo@redhat.com> Signed-off-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20201008161414.2672569-1-philmd@redhat.com Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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- Oct 06, 2020
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Paolo Bonzini authored
Build the library via the main meson.build just like for capstone. This improves the current state of affairs in that we will re-link the qemu executables against a changed libfdt.a, which we wouldn't do before-hand, and lets us remove the whole recursive make machinery. Tested-by:
Richard Henderson <richard.henderson@linaro.org> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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- Oct 03, 2020
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Paolo Bonzini authored
TARGET_BASE_ARCH and TARGET_ABI_DIR are 99% of the time the same as TARGET_ARCH, remove them if so. Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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Paolo Bonzini authored
Replace the individual TARGET_*=y lines with TARGET_ARCH, similar to how TARGET_BASE_ARCH is handled already. Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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Paolo Bonzini authored
We no longer need dummy files to detect targets, since default-configs/targets/ exists. Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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Paolo Bonzini authored
The config-target.mak files are small constant, we can therefore just write them down explicitly. This removes a pretty large part of the configure script, including the whole logic to detect which accelerators are supported by each target. Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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Paolo Bonzini authored
Make room for target files in default-configs/targets/ Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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- Sep 14, 2020
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Havard Skinnemoen authored
This adds two new machines, both supported by OpenBMC: - npcm750-evb: Nuvoton NPCM750 Evaluation Board. - quanta-gsj: A board with a NPCM730 chip. They rely on the NPCM7xx SoC device to do the heavy lifting. They are almost completely identical at the moment, apart from the SoC type, which currently only changes the reset contents of one register (GCR.MDLR), but they might grow apart a bit more as more functionality is added. Both machines can boot the Linux kernel into /bin/sh. Reviewed-by:
Tyrone Ting <kfting@nuvoton.com> Reviewed-by:
Joel Stanley <joel@jms.id.au> Reviewed-by:
Cédric Le Goater <clg@kaod.org> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by:
Alexander Bulekov <alxndr@bu.edu> Signed-off-by:
Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-6-hskinnemoen@google.com Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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- Sep 09, 2020
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Bin Meng authored
This is an initial support for Microchip PolarFire SoC Icicle Kit. The Icicle Kit board integrates a PolarFire SoC, with one SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA. For more details about Microchip PolarFire Soc, please see: https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000. The following perepherals are created as an unimplemented device: - Bus Error Uint 0/1/2/3/4 - L2 cache controller - SYSREG - MPUCFG - IOSCBCFG More devices will be added later. The BIOS image used by this machine is hss.bin, aka Hart Software Services, which can be built from: https://github.com/polarfire-soc/hart-software-services To launch this machine: $ qemu-system-riscv64 -nographic -M microchip-icicle-kit The memory is set to 1 GiB by default to match the hardware. A sanity check on ram size is performed in the machine init routine to prompt user to increase the RAM size to > 1 GiB when less than 1 GiB ram is detected. Signed-off-by:
Bin Meng <bin.meng@windriver.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-5-git-send-email-bmeng.cn@gmail.com> Signed-off-by:
Alistair Francis <alistair.francis@wdc.com>
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- Jul 11, 2020
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Philippe Mathieu-Daudé authored
Arduino boards are build with AVR chipsets. Add some of these boards: - Arduino Duemilanove - Arduino Uno - Arduino Mega For more information: https://www.arduino.cc/en/Main/Products https://store.arduino.cc/arduino-genuino/most-popular [AM: Remove word 'Atmel' from filenames and all elements of code] Suggested-by:
Aleksandar Markovic <aleksandar.m.mail@gmail.com> Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Aleksandar Markovic <aleksandar.m.mail@gmail.com> Reviewed-by:
Igor Mammedov <imammedo@redhat.com> Reviewed-by:
Joaquin de Andres <me@xcancerberox.com.ar> [thuth: sysbus_init_child_obj() ==> object_initialize_child()] Signed-off-by:
Thomas Huth <huth@tuxfamily.org> Message-Id: <20200705140315.260514-26-huth@tuxfamily.org>
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Michael Rolnik authored
Add AVR related definitions into QEMU, make AVR support buildable. [AM: Remove word 'Atmel' from filenames and all elements of code] Suggested-by:
Aleksandar Markovic <aleksandar.m.mail@gmail.com> Signed-off-by:
Michael Rolnik <mrolnik@gmail.com> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Aleksandar Markovic <aleksandar.m.mail@gmail.com> Tested-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by:
Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by:
Thomas Huth <huth@tuxfamily.org> Message-Id: <20200705140315.260514-23-huth@tuxfamily.org> [PMD: Fixed @avr tag in qapi/machine.json] Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org>
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- Jun 22, 2020
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Yoshinori Sato authored
Add the RX machine internally simulated in GDB. Signed-off-by:
Yoshinori Sato <ysato@users.sourceforge.jp> Tested-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> [PMD: Use TYPE_RX62N_CPU, use #define for RX62N_NR_TMR/CMT/SCI, renamed CPU -> MCU, device -> microcontroller] Signed-off-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200224141923.82118-18-ysato@users.sourceforge.jp> [PMD: Split of MCU, rename gdbsim, Add gdbsim-r5f562n7/r5f562n8] Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org>
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- Jun 09, 2020
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Philippe Mathieu-Daudé authored
Use the common API for semihosting logging. Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200603123754.19059-4-f4bug@amsat.org> Signed-off-by:
Laurent Vivier <laurent@vivier.eu>
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- Jun 03, 2020
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Alistair Francis authored
This adds a barebone OpenTitan machine to QEMU. Signed-off-by:
Alistair Francis <alistair.francis@wdc.com> Reviewed-by:
Bin Meng <bin.meng@windriver.com>
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- May 26, 2020
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Philippe Mathieu-Daudé authored
We always miswrote the Fuloong machine... Fix its name. Add an machine alias to the previous name for backward compatibility. Suggested-by:
Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by:
Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-id: <20200526104726.11273-11-f4bug@amsat.org> Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org>
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- May 14, 2020
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Dongjiu Geng authored
This patch builds error_block_address and read_ack_register fields in hardware errors table , the error_block_address points to Generic Error Status Block(GESB) via bios_linker. The max size for one GESB is 1kb, For more detailed information, please refer to document: docs/specs/acpi_hest_ghes.rst Now we only support one Error source, if necessary, we can extend to support more. Suggested-by:
Laszlo Ersek <lersek@redhat.com> Signed-off-by:
Xiang Zheng <zhengxiang9@huawei.com> Reviewed-by:
Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by:
Igor Mammedov <imammedo@redhat.com> Signed-off-by:
Dongjiu Geng <gengdongjiu@huawei.com> Reviewed-by:
Michael S. Tsirkin <mst@redhat.com> Message-id: 20200512030609.19593-5-gengdongjiu@huawei.com Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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- Mar 19, 2020
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Yoshinori Sato authored
Tested-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by:
Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> [PMD: Squashed patches from Richard Henderson modifying qapi/common.json and tests/machine-none-test.c] Message-Id: <20200224141923.82118-21-ysato@users.sourceforge.jp> [PMD: Added @since 5.0 tag in SysEmuTarget] Acked-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org>
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- Mar 12, 2020
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Niek Linnenbank authored
The Allwinner H3 is a System on Chip containing four ARM Cortex A7 processor cores. Features and specifications include DDR2/DDR3 memory, SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and various I/O modules. This commit adds support for the Allwinner H3 System on Chip. Signed-off-by:
Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by:
Alex Bennée <alex.bennee@linaro.org> Tested-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200311221854.30370-2-nieklinnenbank@gmail.com Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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- Mar 05, 2020
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Eric Auger authored
Let's separate the compilation of tpm_tis_common.c from the compilation of tpm_tis_isa.c The common part will be also compiled along with the tpm_tis_sysbus device. Signed-off-by:
Eric Auger <eric.auger@redhat.com> Reviewed-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by:
Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by:
Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 20200305165149.618-5-eric.auger@redhat.com Signed-off-by:
Stefan Berger <stefanb@linux.ibm.com>
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- Feb 20, 2020
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Shivaprasad G Bhat authored
Add support for NVDIMM devices for sPAPR. Piggyback on existing nvdimm device interface in QEMU to support virtual NVDIMM devices for Power. Create the required DT entries for the device (some entries have dummy values right now). The patch creates the required DT node and sends a hotplug interrupt to the guest. Guest is expected to undertake the normal DR resource add path in response and start issuing PAPR SCM hcalls. The device support is verified based on the machine version unlike x86. This is how it can be used .. Ex : For coldplug, the device to be added in qemu command line as shown below -object memory-backend-file,id=memnvdimm0,prealloc=yes,mem-path=/tmp/nvdimm0,share=yes,size=1073872896 -device nvdimm,label-size=128k,uuid=75a3cdd7-6a2f-4791-8d15-fe0a920e8e9e,memdev=memnvdimm0,id=nvdimm0,slot=0 For hotplug, the device to be added from monitor as below object_add memory-backend-file,id=memnvdimm0,prealloc=yes,mem-path=/tmp/nvdimm0,share=yes,size=1073872896 device_add nvdimm,label-size=128k,uuid=75a3cdd7-6a2f-4791-8d15-fe0a920e8e9e,memdev=memnvdimm0,id=nvdimm0,slot=0 Signed-off-by:
Shivaprasad G Bhat <sbhat@linux.ibm.com> Signed-off-by:
Bharata B Rao <bharata@linux.ibm.com> [Early implementation] Message-Id: <158131058078.2897.12767731856697459923.stgit@lep8c.aus.stglabs.ibm.com> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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- Jan 17, 2020
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Alistair Francis authored
Signed-off-by:
Alistair Francis <alistair@alistair23.me> Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Message-id: 49b01423a09cef2ca832ff73a84a996568f1a8fc.1576658572.git.alistair@alistair23.me Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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- Jan 07, 2020
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Philippe Mathieu-Daudé authored
Only the PowerPC e500-based platforms use the MPC I2C controller. Do not build it for the other machines. Signed-off-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191231183216.6781-7-philmd@redhat.com> Acked-by:
David Gibson <david@gibson.dropbear.id.au> Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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- Oct 28, 2019
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Laurent Vivier authored
Inside the 680x0 Macintosh, VIA (Versatile Interface Adapter) is used to interface the keyboard, Mouse, and real-time clock. It also provides control line for the floppy disk driver, video interface, sound circuitry and serial interface. This implementation is based on the MOS6522 object. Co-developed-by:
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by:
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by:
Laurent Vivier <laurent@vivier.eu> Reviewed-by:
Hervé Poussineau <hpoussin@reactos.org> Message-Id: <20191026164546.30020-6-laurent@vivier.eu>
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- Oct 22, 2019
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Sergio Lopez authored
microvm is a machine type inspired by Firecracker and constructed after its machine model. It's a minimalist machine type without PCI nor ACPI support, designed for short-lived guests. microvm also establishes a baseline for benchmarking and optimizing both QEMU and guest operating systems, since it is optimized for both boot time and footprint. Signed-off-by:
Sergio Lopez <slp@redhat.com> Reviewed-by:
Michael S. Tsirkin <mst@redhat.com>
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- Oct 19, 2019
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Max Filippov authored
virt machine is a sim machine with generic PCI host controller. Make common parts of sim machine initialization reusable. Add PCI controller at 0xf0000000 with PIO space at its base address, ECAM space at base address + 1M and MMIO space at base address + 64M. Connect IRQ lines to consecutive CPU external IRQ pins starting from 0. Instantiate network interfaces on virt machine. Xtensa linux kernel configuration virt_defconfig can successfully boot on this machine. Signed-off-by:
Max Filippov <jcmvbkbc@gmail.com>
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- Sep 20, 2019
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Corey Minyard authored
Signed-off-by:
Corey Minyard <cminyard@mvista.com>
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Corey Minyard authored
Pretty straightforward, just hook the current KCS and BT code into the PCI system with the proper configuration. Cc: Michael S. Tsirkin <mst@redhat.com> Cc: M: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Signed-off-by:
Corey Minyard <cminyard@mvista.com>
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- Sep 16, 2019
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Cole Robinson authored
CONFIG_ACPI_PCI is a hard requirement of acpi-build.c, which is built unconditionally for x86 target. Putting it in default-configs/ suggests that it can be easily disabled, which isn't true. Relocate the symbol with the other acpi-build.c requirements, under 'config PC'. This is similar to what is done for the arm 'virt' machine type and CONFIG_ACPI_PCI Signed-off-by:
Cole Robinson <crobinso@redhat.com> Message-Id: <e73e6edff68fd30d69c6a1d02c9ef9192f773c63.1568049871.git.crobinso@redhat.com> Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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- Sep 07, 2019
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Thomas Huth authored
The NeXTcube uses a linear framebuffer with 4 greyscale colors and a fixed resolution of 1120 * 832. This code has been taken from Bryce Lanham's GSoC 2011 NeXT branch at https://github.com/blanham/qemu-NeXT/blob/next-cube/hw/next-fb.c and altered to fit the latest interface of the current QEMU (e.g. the device has been "qdev"-ified etc.). Reviewed-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190831074519.32613-2-huth@tuxfamily.org> Signed-off-by:
Thomas Huth <huth@tuxfamily.org>
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- Jul 02, 2019
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Philippe Mathieu-Daudé authored
This platform use standard PC devices connected to an ISA bus. Networking is provided by a ne2000 chipset. Signed-off-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by:
Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by:
Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190701112612.14758-5-philmd@redhat.com>
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Philippe Mathieu-Daudé authored
The Jazz use the RC4030 Asic to provide an EISA bus and DMA/IRQ. The framebuffer display is managed by a G364, the network card is a Sonic DP83932. A QLogic ESP216 provides a SCSI bus. None, for the both machine variants (PICA-61 and Magnum 4000), the DP83932 chipset is soldered on the board, and is MMIO-mapped (selected via Chip Select). Therefore we have to enforce the 'select' Kconfig rule (we can not use the 'imply' rule helpful when devices are connected on a bus). Reviewed-by:
Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by:
Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190701112612.14758-4-philmd@redhat.com>
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Philippe Mathieu-Daudé authored
The MIPSsim machine only emulates an 8250 UART and a simple network controller, connected via an ISA bus. Reviewed-by:
Thomas Huth <thuth@redhat.com> Signed-off-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by:
Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190701112612.14758-3-philmd@redhat.com>
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Philippe Mathieu-Daudé authored
Disabling the semi-hosting feature leads to build failure: LINK mips-softmmu/qemu-system-mips /usr/bin/ld: target/mips/mips-semi.o: in function `helper_do_semihosting': target/mips/mips-semi.c:335: undefined reference to `qemu_semihosting_log_out' /usr/bin/ld: target/mips/mips-semi.c:338: undefined reference to `qemu_semihosting_log_out' collect2: error: ld returned 1 exit status Add a comment to avoid this feature to be disabled. Signed-off-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by:
Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by:
Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190701112612.14758-2-philmd@redhat.com>
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- Jul 01, 2019
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Hongbo Zhang authored
For AArch64, the existing "virt" machine is primarily meant to run on KVM and execute virtualization workloads, but we need an environment as faithful as possible to physical hardware, for supporting firmware and OS development for physical Aarch64 machines. This patch introduces new machine type 'sbsa-ref' with main features: - Based on 'virt' machine type. - A new memory map. - CPU type cortex-a57. - EL2 and EL3 are enabled. - GIC version 3. - System bus AHCI controller. - System bus EHCI controller. - CDROM and hard disc on AHCI bus. - E1000E ethernet card on PCIE bus. - VGA display adaptor on PCIE bus. - No virtio devices. - No fw_cfg device. - No ACPI table supplied. - Only minimal device tree nodes. Arm Trusted Firmware and UEFI porting to this are done accordingly, and the firmware should supply ACPI tables to the guest OS. The minimal device tree nodes supplied by QEMU for this platform are only to pass the dynamic info reflecting command line input to firmware, not for loading the guest OS. To make the review easier, this task is split into two patches, the fundamental skeleton part and the peripheral devices part; this patch is the first part. Signed-off-by:
Hongbo Zhang <hongbo.zhang@linaro.org> Message-id: 1561890034-15921-2-git-send-email-hongbo.zhang@linaro.org [PMM: commit message tweaks; moved some bits between patch 1 and 2 to ensure patch 1 builds cleanly; removed unneeded lines from Kconfig stanza; only provide board for qemu-system-aarch64, not qemu-system-arm; added MAINTAINERS entry] Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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- May 29, 2019
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Wei Yang authored
Now we have two identical build_mcfg functions. Consolidate them in acpi/pci.c. Signed-off-by:
Wei Yang <richardw.yang@linux.intel.com> v4: * ACPI_PCI depends on both ACPI and PCI * rebase on latest master, adjust arm Kconfig v3: * adjust changelog based on Igor's suggestion Message-Id: <20190521062836.6541-2-richardw.yang@linux.intel.com> Reviewed-by:
Igor Mammedov <imammedo@redhat.com> Reviewed-by:
Michael S. Tsirkin <mst@redhat.com> Signed-off-by:
Michael S. Tsirkin <mst@redhat.com>
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- May 28, 2019
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Alex Bennée authored
There isn't much point building semihosting for platforms that don't support it. Introduce a new symbol and enable it only for the softmmu targets that need it. Signed-off-by:
Alex Bennée <alex.bennee@linaro.org> Reviewed-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org>
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- May 13, 2019
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Thomas Huth authored
The PCI devices should be pulled in by default if PCI_DEVICES is set, so there is no need anymore to enforce them in the configs file. Tested-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by:
Thomas Huth <thuth@redhat.com>
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Thomas Huth authored
This cleans up most settings in default-configs/aarch64-softmmu.mak. Reviewed-by:
Alistair Francis <alistair.francis@wdc.com> Reviewed-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by:
Thomas Huth <thuth@redhat.com>
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