- Jan 13, 2021
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Lukas Straub authored
The yank feature allows to recover from hanging qemu by "yanking" at various parts. Other qemu systems can register themselves and multiple yank functions. Then all yank functions for selected instances can be called by the 'yank' out-of-band qmp command. Available instances can be queried by a 'query-yank' oob command. Signed-off-by:
Lukas Straub <lukasstraub2@web.de> Acked-by:
Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by:
Markus Armbruster <armbru@redhat.com> Message-Id: <69934ceacfd33a7dfe53db145ecc630ad39ee47c.1609167865.git.lukasstraub2@web.de> Acked-by:
Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by:
Markus Armbruster <armbru@redhat.com>
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- Jan 12, 2021
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Yonggang Luo authored
Signed-off-by:
Yonggang Luo <luoyonggang@gmail.com> Reviewed-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210107101919.80-4-luoyonggang@gmail.com> Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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- Jan 06, 2021
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Peter Maydell authored
Currently the PPC UIC ("Universal Interrupt Controller") is implemented as a non-QOM device in ppc4xx_devs.c. Convert it to a proper QOM device in hw/intc. The ppcuic_init() function is retained for the moment with its current interface; in subsequent commits this will be tidied up to avoid the allocation of an irq array. This conversion adds VMState support. It leaves the LOG_UIC() macro as-is to maximise the extent to which this is simply code-movement rather than a rewrite (in new code it would be better to use tracepoints). The default property values for dcr-base and use-vectors are set to match those use by most of our boards with a UIC. Signed-off-by:
Peter Maydell <peter.maydell@linaro.org> Message-Id: <20201212001537.24520-3-peter.maydell@linaro.org> Reviewed-by:
Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by:
Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by:
David Gibson <david@gibson.dropbear.id.au>
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- Jan 04, 2021
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Huacai Chen authored
Add Loongson-3 based machine support, it use liointc as the interrupt controler and use GPEX as the pci controller. Currently it can work with both TCG and KVM. As the machine model is not based on any exiting physical hardware, the name of the machine is "loongson3-virt". It may be superseded in future by a real machine model. If this happens, then a regular deprecation procedure shall occur for "loongson3-virt" machine. We now already have a full functional Linux kernel (based on Linux-5.4.x LTS) here: https://github.com/chenhuacai/linux Of course the upstream kernel is also usable (the kvm host side and guest side have both been upstream in Linux-5.9): https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git How to use QEMU/Loongson-3? 1, Download kernel source from the above URL; 2, Build a kernel with arch/mips/configs/loongson3_defconfig; 3, Boot a Loongson-3A4000 host with this kernel (for KVM mode); 4, Build QEMU-master with this patchset; 5, modprobe kvm (only necessary for KVM mode); 6, Use QEMU with TCG: qemu-system-mips64el -M loongson3-virt,accel=tcg -cpu Loongson-3A1000 -kernel <path_to_kernel> -append ... Use QEMU with KVM: qemu-system-mips64el -M loongson3-virt,accel=kvm -cpu Loongson-3A4000 -kernel <path_to_kernel> -append ... The "-cpu" parameter is optional here and QEMU will use the correct type for TCG/KVM automatically. Co-developed-by:
Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by:
Huacai Chen <chenhuacai@kernel.org> Signed-off-by:
Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201221110538.3186646-5-chenhuacai@kernel.org> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Set TYPE_LOONGSON_MACHINE instance_size in TypeInfo, select FW_CFG_MIPS in Kconfig] Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org>
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Huacai Chen authored
Preparing to add Loongson-3 machine support, add Loongson-3's LEFI (a UEFI-like interface for BIOS-Kernel boot parameters) helpers first. Co-developed-by:
Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by:
Huacai Chen <chenhuacai@kernel.org> Signed-off-by:
Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201221110538.3186646-4-chenhuacai@kernel.org> [PMD: Fixed typo] Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org>
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- Jan 02, 2021
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Richard Henderson authored
This has been a tcg-specific function, but is also in use by hardware accelerators via physmem.c. This can cause link errors when tcg is disabled. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org> Reviewed-by:
Joelle van Dyne <j@getutm.app> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201214140314.18544-3-richard.henderson@linaro.org> Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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- Dec 21, 2020
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Cornelia Huck authored
I push to gitlab anyway to get some CI coverage, so let's make it my primary tree to avoid workflow duplication. Signed-off-by:
Cornelia Huck <cohuck@redhat.com> Acked-by:
Thomas Huth <thuth@redhat.com> Message-Id: <20201214132628.56019-1-cohuck@redhat.com>
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- Dec 18, 2020
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Stefan Hajnoczi authored
The MAINTAINERS file was not updated when the storage daemon was merged. Signed-off-by:
Stefan Hajnoczi <stefanha@redhat.com> Acked-by:
Kevin Wolf <kwolf@redhat.com> Reviewed-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20201209103802.350848-4-stefanha@redhat.com> Signed-off-by:
Kevin Wolf <kwolf@redhat.com>
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- Dec 16, 2020
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Claudio Fontana authored
Signed-off-by:
Claudio Fontana <cfontana@suse.de> Reviewed-by:
Roman Bolshakov <r.bolshakov@yadro.com> Reviewed-by:
Alex Bennée <alex.bennee@linaro.org> Message-Id: <20201212155530.23098-5-cfontana@suse.de> Signed-off-by:
Eduardo Habkost <ehabkost@redhat.com>
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Claudio Fontana authored
Signed-off-by:
Claudio Fontana <cfontana@suse.de> Reviewed-by:
Alex Bennée <alex.bennee@linaro.org> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-4-cfontana@suse.de> Signed-off-by:
Eduardo Habkost <ehabkost@redhat.com>
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Claudio Fontana authored
Signed-off-by:
Claudio Fontana <cfontana@suse.de> Reviewed-by:
Alex Bennée <alex.bennee@linaro.org> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-3-cfontana@suse.de> Signed-off-by:
Eduardo Habkost <ehabkost@redhat.com>
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Claudio Fontana authored
Signed-off-by:
Claudio Fontana <cfontana@suse.de> Reviewed-by:
Alex Bennée <alex.bennee@linaro.org> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201212155530.23098-2-cfontana@suse.de> Signed-off-by:
Eduardo Habkost <ehabkost@redhat.com>
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- Dec 15, 2020
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Alejandro Jimenez authored
Add a QMP command to allow for the behaviors specified by the -no-reboot and -no-shutdown command line option to be set at runtime. The new command is named set-action and takes optional arguments, named after an event, that provide a corresponding action to take. Example: -> { "execute": "set-action", "arguments": { "reboot": "none", "shutdown": "poweroff", "watchdog": "debug" } } <- { "return": {} } Suggested-by:
Paolo Bonzini <pbonzini@redhat.com> Signed-off-by:
Alejandro Jimenez <alejandro.j.jimenez@oracle.com> Message-Id: <1607705564-26264-4-git-send-email-alejandro.j.jimenez@oracle.com> [Split the series differently, with -action based on the QMP command. - Paolo] Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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Eduardo Habkost authored
I'm moving my git repositories to gitlab.com, update MAINTAINERS to point to the correct URL. Signed-off-by:
Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20201214212032.2999853-1-ehabkost@redhat.com> Signed-off-by:
Eduardo Habkost <ehabkost@redhat.com>
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Peter Maydell authored
The Nios2 architecture supports two different interrupt controller options: * The IIC (Internal Interrupt Controller) is part of the CPU itself; it has 32 IRQ input lines and no NMI support. Interrupt status is queried and controlled via the CPU's ipending and istatus registers. * The EIC (External Interrupt Controller) interface allows the CPU to connect to an external interrupt controller. The interface allows the interrupt controller to present a packet of information containing: - handler address - interrupt level - register set - NMI mode QEMU does not model an EIC currently. We do model the IIC, but its implementation is split across code in hw/nios2/cpu_pic.c and hw/intc/nios2_iic.c. The code in those two files has no state of its own -- the IIC state is in the Nios2CPU state struct. Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they can have GPIO input lines themselves, so we can implement the IIC directly in the CPU object the same way that real hardware does. Create named "IRQ" GPIO inputs to the Nios2 CPU object, and make the only user of the IIC wire up directly to those instead. Note that the old code had an "NMI" concept which was entirely unused and also as far as I can see not architecturally correct, since only the EIC has a concept of an NMI. This fixes a Coverity-reported trivial memory leak of the IRQ array allocated in nios2_cpu_pic_init(). Fixes: Coverity CID 1421916 Signed-off-by:
Peter Maydell <peter.maydell@linaro.org> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201129174022.26530-2-peter.maydell@linaro.org Reviewed-by:
Wentong Wu <wentong.wu@intel.com> Tested-by:
Wentong Wu <wentong.wu@intel.com>
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- Dec 14, 2020
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David Gibson authored
Greg has agreed to be co-maintainer of the ppc target and machines. This should avoid repeats of the problem we had in qemu-5.2 where a last minute fix was needed while I was on holiday. Signed-off-by:
David Gibson <david@gibson.dropbear.id.au> Acked-by:
Greg Kurz <groug@kaod.org>
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- Dec 13, 2020
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Michael Roth authored
I've recently switched employers and the current email address is out of date. Signed-off-by:
Michael Roth <michael.roth@amd.com> Reviewed-by:
Thomas Huth <thuth@redhat.com> Message-Id: <20201027060253.353054-1-michael.roth@amd.com> Signed-off-by:
Laurent Vivier <laurent@vivier.eu>
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Huacai Chen authored
Use @kernel.org address as the main communications end point. Update the corresponding M-entries and .mailmap (for git shortlog translation). Signed-off-by:
Huacai Chen <chenhuacai@kernel.org> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1607160121-9977-1-git-send-email-chenhuacai@kernel.org>
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- Dec 11, 2020
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Hanna Reitz authored
block-export-add type=fuse allows mounting block graph nodes via FUSE on some existing regular file. That file should then appears like a raw disk image, and accesses to it result in accesses to the exported BDS. Right now, we only implement the necessary block export functions to set it up and shut it down. We do not implement any access functions, so accessing the mount point only results in errors. This will be addressed by a followup patch. We keep a hash table of exported mount points, because we want to be able to detect when users try to use a mount point twice. This is because we invoke stat() to check whether the given mount point is a regular file, but if that file is served by ourselves (because it is already used as a mount point), then this stat() would have to be served by ourselves, too, which is impossible to do while we (as the caller) are waiting for it to settle. Therefore, keep track of mount point paths to at least catch the most obvious instances of that problem. Signed-off-by:
Max Reitz <mreitz@redhat.com> Message-Id: <20201027190600.192171-3-mreitz@redhat.com> Signed-off-by:
Kevin Wolf <kwolf@redhat.com>
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Cornelia Huck authored
This adds a very basic test for checking that we present devices in a way that Linux can consume: boot with both virtio-net-ccw and virtio-net-pci attached and then verify that Linux is able to see and detect these devices. Signed-off-by:
Cornelia Huck <cohuck@redhat.com> Reviewed-by:
Thomas Huth <thuth@redhat.com> Reviewed-by:
Wainer dos Santos Moschetta <wainersm@redhat.com> Message-Id: <20201126130158.1471985-1-cohuck@redhat.com>
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- Dec 10, 2020
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Sunil Muthuswamy authored
This patch adds support the kernel-irqchip option for WHPX with on or off value. 'split' value is not supported for the option. The option only works for the latest version of Windows (ones that are coming out on Insiders). The change maintains backward compatibility on older version of Windows where this option is not supported. Signed-off-by:
Sunil Muthuswamy <sunilmut@microsoft.com> Message-Id: <SN4PR2101MB0880B13258DA9251F8459F4DC0170@SN4PR2101MB0880.namprd21.prod.outlook.com> Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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Vikram Garhwal authored
Reviewed-by:
Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by:
Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by:
Vikram Garhwal <fnu.vikram@xilinx.com> Message-id: 1605728926-352690-5-git-send-email-fnu.vikram@xilinx.com Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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- Nov 23, 2020
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Philippe Mathieu-Daudé authored
Document the following Raspberry Pi models: - raspi0 Raspberry Pi Zero (revision 1.2) - raspi1ap Raspberry Pi A+ (revision 1.1) - raspi2b Raspberry Pi 2B (revision 1.1) - raspi3ap Raspberry Pi 3A+ (revision 1.0) - raspi3b Raspberry Pi 3B (revision 1.2) Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201120173953.2539469-3-f4bug@amsat.org Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Philippe Mathieu-Daudé authored
Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201120154545.2504625-7-f4bug@amsat.org Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Philippe Mathieu-Daudé authored
Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201120154545.2504625-6-f4bug@amsat.org Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Philippe Mathieu-Daudé authored
Fixes: 0553ef42 ("docs: add Orange Pi PC document") Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20201120154545.2504625-5-f4bug@amsat.org Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Philippe Mathieu-Daudé authored
Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201120154545.2504625-4-f4bug@amsat.org Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Philippe Mathieu-Daudé authored
Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Cédric Le Goater <clg@kaod.org> Message-id: 20201120154545.2504625-3-f4bug@amsat.org Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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Philippe Mathieu-Daudé authored
Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201120154545.2504625-2-f4bug@amsat.org Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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- Nov 13, 2020
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Richard Henderson authored
Consolidate all of my MAINTAINERS entries on my work address. Signed-off-by:
Richard Henderson <richard.henderson@linaro.org>
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- Nov 10, 2020
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Alexander Bulekov authored
Signed-off-by:
Alexander Bulekov <alxndr@bu.edu> Message-Id: <20201106180600.360110-2-alxndr@bu.edu> Signed-off-by:
Thomas Huth <thuth@redhat.com>
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Philippe Mathieu-Daudé authored
Do not let the gitlab-pipeline-status script unmaintained, add it to the 'GitLab Continuous Integration' section. Fixes: c02b2eac ("GitLab Gating CI: introduce pipeline-status contrib script") Signed-off-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20201108204535.2319870-5-philmd@redhat.com> Reviewed-by:
Wainer dos Santos Moschetta <wainersm@redhat.com> Signed-off-by:
Thomas Huth <thuth@redhat.com>
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- Nov 09, 2020
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Markus Armbruster authored
Add the relevant QAPI schema modules to section Audio, QMP, Tracing, Cryptography. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Stefan Hajnoczi <stefanha@redhat.com> Cc: Daniel P. Berrange <berrange@redhat.com> Signed-off-by:
Markus Armbruster <armbru@redhat.com> Message-Id: <20201102081550.171061-2-armbru@redhat.com> Reviewed-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by:
Stefan Hajnoczi <stefanha@redhat.com> Acked-by:
Daniel P. Berrangé <berrange@redhat.com>
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- Nov 08, 2020
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Philippe Mathieu-Daudé authored
To be fair with other subsystems listed as 'Odd Fixes' but having maintainers more present, demote the Renesas sections from being 'Maintained' to 'Odd Fixes' (has a maintainer but they don't have time to do much other than throw the odd patch in.) This matches Magnus's possibilities so far: https://www.mail-archive.com/qemu-devel@nongnu.org/msg710319.html Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Thomas Huth <thuth@redhat.com> Message-Id: <20201102104001.2062572-1-f4bug@amsat.org>
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Philippe Mathieu-Daudé authored
The nanoMIPS ISA has been announced in 2018 for various projects: GCC: https://gcc.gnu.org/legacy-ml/gcc/2018-05/msg00012.html Linux: https://lwn.net/Articles/753605/ QEMU: https://www.mail-archive.com/qemu-devel@nongnu.org/msg530721.html Unfortunately the links referenced doesn't work anymore (www.mips.com). From this Wayback machine link [1] we can get to a working place to download a toolchain (a more recent release than the one referenced in the announcement mails): http://codescape.mips.com/components/toolchain/nanomips/2018.04-02/downloads.html The toolchain page mention LLVM but simply links http://llvm.org/ where there is no reference on nanoMIPS. The only reference in the GCC mailing list, is the nanoMIPS announcement: https://gcc.gnu.org/pipermail/gcc/2018-May.txt The developer who authored the announcements have been emailed [2] to ask for more information but all their emails are now bouncing: - Your message to Stefan.Markovic@mips.com couldn't be delivered. - Your message to smarkovic@wavecomp.com couldn't be delivered. - Couldn't deliver the message to the following recipients: Robert.Suchanek@mips.com, matthew.fortune@mips.com, marcin.nowakowski@mips.com Our deprecation policy do not allow feature removal before 2 release, therefore declare the nanoMIPS ISA code deprecated as of QEMU 5.2. This gives time to developers to update the QEMU community, or interested parties to step in to maintain this code. [1] https://web.archive.org/web/20180904044530/https://www.mips.com/develop/tools/compilers/ [2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg756392.html Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by:
Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201102202710.2224691-1-f4bug@amsat.org>
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- Nov 03, 2020
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Philippe Mathieu-Daudé authored
The "block/nvme.h" header is shared by both the NVMe block driver and the NVMe emulated device. Add the 'F:' entry on both sections, so all maintainers/reviewers are notified when it is changed. Signed-off-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by:
Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by:
Klaus Jensen <k.jensen@samsung.com> Message-Id: <20200701140634.25994-1-philmd@redhat.com>
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Philippe Mathieu-Daudé authored
We deprecated the support for the 'r4k' machine for the 5.0 release (commit d32dc614), which means that our deprecation policy allows us to drop it in release 5.2. Remove the code. To repeat the rationale from the deprecation note: - this virtual machine has no specification - the Linux kernel dropped support for it 10 years ago Users are recommended to use the Malta board instead. Acked-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Thomas Huth <thuth@redhat.com> ACKed-by:
Peter Krempa <pkrempa@redhat.com> Message-Id: <20201102201311.2220005-1-f4bug@amsat.org>
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Bin Meng authored
This creates a minimum model for Microchip PolarFire SoC SYSREG module. It only implements the ENVM_CR register to tell guest software that eNVM is running at the configured divider rate. Signed-off-by:
Bin Meng <bin.meng@windriver.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com> Message-id: 1603863010-15807-7-git-send-email-bmeng.cn@gmail.com Signed-off-by:
Alistair Francis <alistair.francis@wdc.com>
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Bin Meng authored
This creates a model for PolarFire SoC IOSCB [1] module. It actually contains lots of sub-modules like various PLLs to control different peripherals. Only the mininum capabilities are emulated to make the HSS DDR memory initialization codes happy. Lots of sub-modules are created as an unimplemented devices. [1] PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm in https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map Signed-off-by:
Bin Meng <bin.meng@windriver.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com> Message-id: 1603863010-15807-5-git-send-email-bmeng.cn@gmail.com Signed-off-by:
Alistair Francis <alistair.francis@wdc.com>
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Bin Meng authored
The PolarFire SoC DDR Memory Controller mainly includes 2 modules, called SGMII PHY module and the CFG module, as documented in the chipset datasheet. This creates a single file that groups these 2 modules, providing the minimum functionalities that make the HSS DDR initialization codes happy. Signed-off-by:
Bin Meng <bin.meng@windriver.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com> Message-id: 1603863010-15807-3-git-send-email-bmeng.cn@gmail.com Signed-off-by:
Alistair Francis <alistair.francis@wdc.com>
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