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  1. Feb 29, 2016
  2. Feb 28, 2016
  3. Feb 26, 2016
    • Peter Maydell's avatar
      Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160226' into staging · 6e378dd2
      Peter Maydell authored
      
      target-arm queue:
       * Clean up handling of bad mode switches writing to CPSR, and implement
         the ARMv8 requirement that they set PSTATE.IL
       * Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps on perf monitor
         register accesses
       * Don't implement stellaris-pl061-only registers on generic-pl061
       * Fix SD card handling for raspi
       * Add missing include files to MAINTAINERS
       * Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW
       * Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF
      
      # gpg: Signature made Fri 26 Feb 2016 15:19:07 GMT using RSA key ID 14360CDE
      # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
      # gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
      # gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
      
      * remotes/pmaydell/tags/pull-target-arm-20160226:
        target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF
        target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW
        sdhci: add quirk property for card insert interrupt status on Raspberry Pi
        sdhci: Revert "add optional quirk property to disable card insertion/removal interrupts"
        MAINTAINERS: Add some missing ARM related header files
        raspi: fix SD card with recent sdhci changes
        ARM: PL061: Checking register r/w accesses to reserved area
        target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps
        target-arm: Fix handling of SDCR for 32-bit code
        target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1
        target-arm: Make mode switches from Hyp via CPS and MRS illegal
        target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL
        target-arm: Forbid mode switch to Mon from Secure EL1
        target-arm: Add Hyp mode checks to bad_mode_switch()
        target-arm: Add comment about not implementing NSACR.RFR
        target-arm: In cpsr_write() ignore mode switches from User mode
        linux-user: Use restrictive mask when calling cpsr_write()
        target-arm: Raw CPSR writes should skip checks and bank switching
        target-arm: Add write_type argument to cpsr_write()
        target-arm: Give CPSR setting on 32-bit exception return its own helper
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      6e378dd2
    • Peter Maydell's avatar
      Merge remote-tracking branch 'remotes/amit-migration/tags/migration-for-2.6-5' into staging · aa53d5bf
      Peter Maydell authored
      
      migration pull
       - fix a qcow2 assert
       - fix for older distros (CentOS 5)
       - documentation for vmstate flags
       - minor code rearrangement
      
      # gpg: Signature made Fri 26 Feb 2016 15:15:15 GMT using RSA key ID 854083B6
      # gpg: Good signature from "Amit Shah <amit@amitshah.net>"
      # gpg:                 aka "Amit Shah <amit@kernel.org>"
      # gpg:                 aka "Amit Shah <amitshah@gmx.net>"
      
      * remotes/amit-migration/tags/migration-for-2.6-5:
        migration (postcopy): move bdrv_invalidate_cache_all of of coroutine context
        migration (ordinary): move bdrv_invalidate_cache_all of of coroutine context
        migration/vmstate: document VMStateFlags
        MAINTAINERS: Add docs/migration.txt to the "Migration" section
        migration/postcopy-ram: Guard use of sys/eventfd.h with CONFIG_EVENTFD
        migration: reorder code to make it symmetric
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      aa53d5bf
    • Denis V. Lunev's avatar
      migration (postcopy): move bdrv_invalidate_cache_all of of coroutine context · ea6a55bc
      Denis V. Lunev authored
      
      There is a possibility to hit an assert in qcow2_get_specific_info that
      s->qcow_version is undefined. This happens when VM in starting from
      suspended state, i.e. it processes incoming migration, and in the same
      time 'info block' is called.
      
      The problem is that qcow2_invalidate_cache() closes the image and
      memset()s BDRVQcowState in the middle.
      
      The patch moves processing of bdrv_invalidate_cache_all out of
      coroutine context for postcopy migration to avoid that. This function
      is called with the following stack:
        process_incoming_migration_co
        qemu_loadvm_state
        qemu_loadvm_state_main
        loadvm_process_command
        loadvm_postcopy_handle_run
      
      Signed-off-by: default avatarDenis V. Lunev <den@openvz.org>
      Tested-by: default avatarDr. David Alan Gilbert <dgilbert@redhat.com>
      Reviewed-by: default avatarFam Zheng <famz@redhat.com>
      CC: Paolo Bonzini <pbonzini@redhat.com>
      CC: Juan Quintela <quintela@redhat.com>
      CC: Amit Shah <amit.shah@redhat.com>
      Message-Id: <1456304019-10507-3-git-send-email-den@openvz.org>
      Signed-off-by: default avatarAmit Shah <amit.shah@redhat.com>
      ea6a55bc
    • Denis V. Lunev's avatar
      migration (ordinary): move bdrv_invalidate_cache_all of of coroutine context · 0aa6aefc
      Denis V. Lunev authored
      
      There is a possibility to hit an assert in qcow2_get_specific_info that
      s->qcow_version is undefined. This happens when VM in starting from
      suspended state, i.e. it processes incoming migration, and in the same
      time 'info block' is called.
      
      The problem is that qcow2_invalidate_cache() closes the image and
      memset()s BDRVQcowState in the middle.
      
      The patch moves processing of bdrv_invalidate_cache_all out of
      coroutine context for standard migration to avoid that.
      
      Signed-off-by: default avatarDenis V. Lunev <den@openvz.org>
      Reviewed-by: default avatarFam Zheng <famz@redhat.com>
      CC: Paolo Bonzini <pbonzini@redhat.com>
      CC: Juan Quintela <quintela@redhat.com>
      CC: Amit Shah <amit.shah@redhat.com>
      Message-Id: <1456304019-10507-2-git-send-email-den@openvz.org>
      
      [Amit: Fix a use-after-free bug]
      
      Signed-off-by: default avatarAmit Shah <amit.shah@redhat.com>
      0aa6aefc
    • Peter Maydell's avatar
      target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF · e20d84c1
      Peter Maydell authored
      
      The v8 ARM ARM defines that unused spaces in the ID_AA64* system
      register ranges are Reserved and must RAZ, rather than being UNDEF.
      Implement this.
      
      In particular, ARM v8.2 adds a new feature register ID_AA64MMFR2,
      and newer versions of the Linux kernel will attempt to read this,
      which causes them not to boot up on versions of QEMU missing this fix.
      
      Since the encoding .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6
      is actually defined in ARMv8 (as ID_MMFR4), we give it an entry in
      the ARMCPU struct so CPUs can override it, though since none do
      this too will just RAZ.
      
      Cc: qemu-stable@nongnu.org
      Reported-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Message-id: 1455890863-11203-1-git-send-email-peter.maydell@linaro.org
      Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
      Tested-by: default avatarAlex Bennée <alex.bennee@linaro.org>
      e20d84c1
    • Edgar E. Iglesias's avatar
      target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW · d44ec156
      Edgar E. Iglesias authored
      
      Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW due to the register not
      having any underlying state. This fixes an issue with booting
      KVM enabled kernels when EL2 is on.
      
      Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
      Message-id: 1456490739-19343-1-git-send-email-edgar.iglesias@gmail.com
      Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      d44ec156
    • Andrew Baumann's avatar
      sdhci: add quirk property for card insert interrupt status on Raspberry Pi · 0a7ac9f9
      Andrew Baumann authored
      
      This quirk is a workaround for the following hardware behaviour, on
      which UEFI (specifically, the bootloader for Windows on Pi2) depends:
      
      1. at boot with an SD card present, the interrupt status/enable
         registers are initially zero
      2. upon enabling it in the interrupt enable register, the card insert
         bit in the interrupt status register is immediately set
      3. after a subsequent controller reset, the card insert interrupt does
         not fire, even if enabled in the interrupt enable register
      
      Signed-off-by: default avatarAndrew Baumann <Andrew.Baumann@microsoft.com>
      Message-id: 1456436130-7048-3-git-send-email-Andrew.Baumann@microsoft.com
      Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      0a7ac9f9
    • Andrew Baumann's avatar
      sdhci: Revert "add optional quirk property to disable card insertion/removal interrupts" · 5c1bc9a2
      Andrew Baumann authored
      
      This reverts commit 72369755.
      
      This change was poorly tested on my part. It squelched card insertion
      interrupts on reset, but that was not necessary because sdhci_reset()
      clears all the registers (via the call to memset), so the subsequent
      sdhci_insert_eject_cb() call never sees the card insert interrupt
      enabled. However, not calling the insert_eject_cb results in prnsts
      remaining 0, when it actually needs to be updated to indicate card
      presence and R/O status.
      
      Signed-off-by: default avatarAndrew Baumann <Andrew.Baumann@microsoft.com>
      Message-id: 1456436130-7048-2-git-send-email-Andrew.Baumann@microsoft.com
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      5c1bc9a2
    • Thomas Huth's avatar
      MAINTAINERS: Add some missing ARM related header files · ed0db866
      Thomas Huth authored
      
      Some header files in the include/hw/arm/ directory can be assigned
      to entries in the MAINTAINERS file.
      
      Signed-off-by: default avatarThomas Huth <thuth@redhat.com>
      Message-id: 1456399324-24259-1-git-send-email-thuth@redhat.com
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      ed0db866
    • Andrew Baumann's avatar
      raspi: fix SD card with recent sdhci changes · a55b53a2
      Andrew Baumann authored
      
      Recent changes to sdhci broke SD on raspi. This change mirrors
      the logic to create the SD card device at the board level.
      
      Signed-off-by: default avatarAndrew Baumann <Andrew.Baumann@microsoft.com>
      Message-id: 1456351128-5560-1-git-send-email-Andrew.Baumann@microsoft.com
      Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      a55b53a2
    • Wei Huang's avatar
      ARM: PL061: Checking register r/w accesses to reserved area · 09aa3bf3
      Wei Huang authored
      
      pl061.c emulates two GPIO devices, ARM PL061 and TI Stellaris, which
      share the same read/write functions (pl061_read and pl061_write).
      However PL061 and Stellaris have different GPIO register definitions
      and pl061_read()/pl061_write() doesn't check it. This patch enforces
      checking on offset, preventing R/W into the reserved memory area.
      
      Signed-off-by: default avatarWei Huang <wei@redhat.com>
      Message-id: 1455814580-17699-1-git-send-email-wei@redhat.com
      Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      09aa3bf3
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