- Aug 28, 2023
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Paolo Bonzini authored
This reverts commit e8e4298f. ensuregroup allows to specify both the acceptable versions of avocado, and a locked version to be used when avocado is not installed as a system pacakge. This lets us install avocado in pyvenv/ using "mkvenv.py" and reuse the distro package on Fedora and CentOS Stream (the only distros where it's available). ensuregroup's usage of "(>=..., <=...)" constraints when evaluating the distro package, and "==" constraints when installing it from PyPI, makes it possible to avoid conflicts between the known-good version and a package plugins included in the distro. This is because package plugins have "==" constraints on the version that is included in the distro, and, using "pip install avocado==88.1" on a venv that includes system packages will result in an error: avocado-framework-plugin-varianter-yaml-to-mux 98.0 requires avocado-framework==98.0, but you have avocado-framework 88.1 which is incompatible. avocado-framework-plugin-result-html 98.0 requires avocado-framework==98.0, but you have avocado-framework 88.1 which is incompatible. But at the same time, if the venv does not include a system distribution of avocado then we can install a known-good version and stick to LTS releases. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1663 Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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Paolo Bonzini authored
Using the new ensuregroup command, the desired versions of meson and sphinx can be placed in pythondeps.toml rather than configure. The meson.install entry in pythondeps.toml matches the version that is found in python/wheels. This ensures that mkvenv.py uses the bundled wheel even if PyPI is enabled; thus not introducing warnings or errors from versions that are more recent than the one used in CI. The sphinx entries match what is shipped in Fedora 38. It's the last release that has support for older versions of Python (sphinx 6.0 requires Python 3.8) and especially docutils (of which sphinx 6.0 requires version 0.18). This is important because Ubuntu 20.04 has docutils 0.14 and Debian 11 has docutils 0.16. "mkvenv.py ensure" is only used to bootstrap tomli. Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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Paolo Bonzini authored
Debian only introduced tomli in the bookworm release. Use a vendored wheel to avoid requiring a package that is only in bullseye-backports and is also absent in Ubuntu 20.04. While at it, fix an issue in the vendor.py scripts which does not add a newline after each package and hash. Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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Paolo Bonzini authored
Since there is a vendored copy, there is no point in choosing online operation. Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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Paolo Bonzini authored
This brings in a newer version of the pipewire mapping, so rename it. Python 3.9 and 3.10 do not seem to work in OpenSUSE LEAP 15.5 (weird, because 3.9 persisted from 15.3 to 15.4) so bump the Python runtime version to 3.11. Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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Paolo Bonzini authored
Introduce a new subcommand that retrieves the packages to be installed from a TOML file. This allows being more flexible in using the system version of a package, while at the same time using a known-good version when installing the package. This is important for packages that sometimes have backwards-incompatible changes or that depend on specific versions of their dependencies. Compared to JSON, TOML is more human readable and easier to edit. A parser is available in 3.11 but also available as a small (12k) package for older versions, tomli. While tomli is bundled with pip, this is only true of recent versions of pip. Of all the supported OSes pretty much only FreeBSD has a recent enough version of pip while staying on Python <3.11. So we cannot use the same trick that is in place for distlib. Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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Paolo Bonzini authored
We would like to place all Python dependencies in the same file, so that we can add more information without having long and complex command lines. The plan is to have a TOML file with one entry per package, for example [avocado] avocado-framework = { accepted = "(>=88.1, <93.0)", installed = "88.1", canary = "avocado" } Each TOML section will thus be a dictionary of dictionaries. Modify mkvenv.py's workhorse function, _do_ensure, to already operate on such a data structure. The "ensure" subcommand is modified to separate the depspec into a name and a version part, and use the result (plus the --diagnose argument) to build a dictionary for each command line argument. Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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Paolo Bonzini authored
Move the matching between the "absent" array and dep_specs[0] inside the loop, preparing for the possibility of having multiple canaries among the installed packages. Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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Paolo Bonzini authored
With the release of version 12 on June 10, 2023, Debian 10 is not supported anymore. Modify the cross compiler container to build on a newer version. Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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Paolo Bonzini authored
The tricore tools are not detected when they are installed in the host system, only if they are taken from an external container. For this reason the build-tricore-softmmu job was not running the TCG tests. In addition the container provides all tools, not just as/ld/gcc, so there is no need to special case tricore. Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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- Aug 24, 2023
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Stefan Hajnoczi authored
Merge tag 'pull-target-arm-20230824' of https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/gpio/nrf51: implement DETECT signal * accel/kvm: Specify default IPA size for arm64 * ptw: refactor, fix some FEAT_RME bugs * target/arm: Adjust PAR_EL1.SH for Device and Normal-NC memory types * target/arm/helper: Implement CNTHCTL_EL2.CNT[VP]MASK * Fix SME ST1Q * Fix 64-bit SSRA # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmTnIoUZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3vufEACPJcwyFvSBHDv4VQ6tbgOU # zwjpUMv4RMKhCOjuxBlJ2DICwOcGNuKer0tc6wkH2T5Ebhoego1osYbRZZoawAJf # ntg+Ndrx1QH9ORuGqYccLXtHnP741KiKggDHM05BJqB7rqtuH+N4fEn7Cdsw/DNg # XuCYD5QrxMYvkSOD1l8W0aqp81ucYPgkFqLufypgxrXUiRZ1RBAmPF47BFFdnM8f # NmrmT1LTF5jr70ySRB+ukK6BAGDc0CUfs6R6nYRwUjRPmSG2rrtUDGo+nOQGDqJo # PHWmt7rdZQG2w7HVyE/yc3h/CQ3NciwWKbCkRlaoujxHx/B6DRynSeO3NXsP8ELu # Gizoi3ltwHDQVIGQA19P5phZKHZf7x3MXmK4fDBGB9znvoSFTcjJqkdaN/ARXXO3 # e1vnK1MqnPI8Z1nGdeVIAUIrqhtLHnrrM7jf1tI/e4sjpl3prHq2PvQkakXu8clr # H8bPZ9zZzyrrSbl4NhpaFTsUiYVxeLoJsNKAmG8dHb+9YsFGXTvEBhtR9eUxnbaV # XyZ3jEdeW7/ngQ4C6XMD2ZDiKVdx2xJ2Pp5npvljldjmtGUvwQabKo+fPDt2fKjM # BwjhHA50I633k4fYIwm8YOb70I4oxoL9Lr6PkKriWPMTI5r7+dtwgigREVwnCn+Y # RsiByKMkDO2TcoQjvBZlCA== # =3MJ8 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 24 Aug 2023 05:27:33 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20230824' of https://git.linaro.org/people/pmaydell/qemu-arm : (35 commits) target/arm: Fix 64-bit SSRA target/arm: Fix SME ST1Q target/arm/helper: Implement CNTHCTL_EL2.CNT[VP]MASK target/arm/helper: Check SCR_EL3.{NSE, NS} encoding for AT instructions target/arm: Pass security space rather than flag for AT instructions target/arm: Skip granule protection checks for AT instructions target/arm/helper: Fix tlbmask and tlbbits for TLBI VAE2* target/arm/ptw: Load stage-2 tables from realm physical space target/arm: Adjust PAR_EL1.SH for Device and Normal-NC memory types target/arm/ptw: Report stage 2 fault level for stage 2 faults on stage 1 ptw target/arm/ptw: Check for block descriptors at invalid levels target/arm/ptw: Set attributes correctly for MMU disabled data accesses target/arm/ptw: Drop S1Translate::out_secure target/arm/ptw: Remove S1Translate::in_secure target/arm/ptw: Remove last uses of ptw->in_secure target/arm/ptw: Only fold in NSTable bit effects in Secure state target/arm: Pass an ARMSecuritySpace to arm_is_el2_enabled_secstate() target/arm/ptw: Pass an ARMSecuritySpace to arm_hcr_el2_eff_secstate() target/arm/ptw: Pass ARMSecurityState to regime_translation_disabled() target/arm/ptw: Pass ptw into get_phys_addr_pmsa*() and get_phys_addr_disabled() ... Signed-off-by:
Stefan Hajnoczi <stefanha@redhat.com>
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https://gitlab.com/gaosong/qemuStefan Hajnoczi authored
pull-loongarch-20230824 # -----BEGIN PGP SIGNATURE----- # # iLMEAAEIAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZOcdAwAKCRBAov/yOSY+ # 3w3CA/sH8+Ay+Qnaqa2vEyuhOlFQuxHKeR7mYfsitAdzh8yMK2K8C2iBUzDzL1H3 # kZmZbCcYX7ko9RLhsuXmvfBJ7iwzY55ozSHLIjJ/VS4JVE5B0cUSZ5jjIPDqpzDs # 7TUt9qpTkwg0e+klzVREWLSWP5xopvkRvFHZM3KZZhGMphOTUQ== # =/HHZ # -----END PGP SIGNATURE----- # gpg: Signature made Thu 24 Aug 2023 05:04:03 EDT # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20230824' of https://gitlab.com/gaosong/qemu : (31 commits) hw/loongarch: Fix ACPI processor id off-by-one error target/loongarch: Split fcc register to fcc0-7 in gdbstub hw/intc/loongarch_pch: fix edge triggered irq handling target/loongarch: cpu: Implement get_arch_id callback target/loongarch: Add avail_IOCSR to check iocsr instructions target/loongarch: Add avail_LSX to check LSX instructions target/loongarch: Add avail_LAM to check atomic instructions target/loongarch: Add avail_LSPW to check LSPW instructions target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions hw/loongarch: Remove restriction of la464 cores in the virt machine target/loongarch: Add LoongArch32 cpu la132 target/loongarch: Add avail_64 to check la64-only instructions target/loongarch: Add a check parameter to the TRANS macro target/loongarch: Sign extend results in VA32 mode target/loongarch: Truncate high 32 bits of address in VA32 mode target/loongarch: Extract set_pc() helper target/loongarch: Extract make_address_pc() helper target/loongarch: Extract make_address_i() helper target/loongarch: Extract make_address_x() helper target/loongarch: Add LA64 & VA32 to DisasContext ... Signed-off-by:
Stefan Hajnoczi <stefanha@redhat.com>
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Jiajie Chen authored
In hw/acpi/aml-build.c:build_pptt() function, the code assumes that the ACPI processor id equals to the cpu index, for example if we have 8 cpus, then the ACPI processor id should be in range 0-7. However, in hw/loongarch/acpi-build.c:build_madt() function we broke the assumption. If we have 8 cpus again, the ACPI processor id in MADT table would be in range 1-8. It violates the following description taken from ACPI spec 6.4 table 5.138: If the processor structure represents an actual processor, this field must match the value of ACPI processor ID field in the processor’s entry in the MADT. It will break the latest Linux 6.5-rc6 with the following error message: ACPI PPTT: PPTT table found, but unable to locate core 7 (8) Invalid BIOS PPTT Here 7 is the last cpu index, 8 is the ACPI processor id learned from MADT. With this patch, Linux can properly detect SMT threads when "-smp 8,sockets=1,cores=4,threads=2" is passed: Thread(s) per core: 2 Core(s) per socket: 2 Socket(s): 2 The detection of number of sockets is still wrong, but that is out of scope of the commit. Signed-off-by:
Jiajie Chen <c@jia.je> Reviewed-by:
Bibo Mao <maobibo@loongson.cn> Message-Id: <20230820105658.99123-2-c@jia.je> Signed-off-by:
Song Gao <gaosong@loongson.cn>
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Jiajie Chen authored
Since GDB 13.1(GDB commit ea3352172), GDB LoongArch changed to use fcc0-7 instead of fcc register. This commit partially reverts commit 2f149c75 (`target/loongarch: Update gdb_set_fpu() and gdb_get_fpu()`) to match the behavior of GDB. Note that it is a breaking change for GDB 13.0 or earlier, but it is also required for GDB 13.1 or later to work. Signed-off-by:
Jiajie Chen <c@jia.je> Acked-by:
Song Gao <gaosong@loongson.cn> Message-Id: <20230808054315.3391465-1-c@jia.je> Signed-off-by:
Song Gao <gaosong@loongson.cn>
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Bibo Mao authored
For edge triggered irq, qemu_irq_pulse is used to inject irq. It will set irq with high level and low level soon to simluate pulse irq. For edge triggered irq, irq is injected and set as pending at rising level, do not clear irq at lowering level. LoongArch pch interrupt will clear irq for lowering level irq, there will be problem. ACPI ged deivce is edge-triggered irq, it is used for cpu/memory hotplug. This patch fixes memory hotplug issue on LoongArch virt machine. Signed-off-by:
Bibo Mao <maobibo@loongson.cn> Reviewed-by:
Song Gao <gaosong@loongson.cn> Message-Id: <20230707091557.1474790-1-maobibo@loongson.cn> Signed-off-by:
Song Gao <gaosong@loongson.cn>
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Bibo Mao authored
Implement the callback for getting the architecture-dependent CPU ID, the cpu ID is physical id described in ACPI MADT table, this will be used for cpu hotplug. Signed-off-by:
Bibo Mao <maobibo@loongson.cn> Reviewed-by:
Song Gao <gaosong@loongson.cn> Message-Id: <20230824005007.2000525-1-maobibo@loongson.cn> Signed-off-by:
Song Gao <gaosong@loongson.cn>
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Song Gao authored
Signed-off-by:
Song Gao <gaosong@loongson.cn> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-16-gaosong@loongson.cn> Message-Id: <20230822072219.35719-1-philmd@linaro.org>
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Song Gao authored
Signed-off-by:
Song Gao <gaosong@loongson.cn> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-15-gaosong@loongson.cn> Message-Id: <20230822073026.35776-1-philmd@linaro.org>
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Song Gao authored
Signed-off-by:
Song Gao <gaosong@loongson.cn> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-14-gaosong@loongson.cn> Message-Id: <20230822071959.35620-8-philmd@linaro.org>
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Song Gao authored
Signed-off-by:
Song Gao <gaosong@loongson.cn> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-13-gaosong@loongson.cn> Message-Id: <20230822071959.35620-7-philmd@linaro.org>
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Song Gao authored
Signed-off-by:
Song Gao <gaosong@loongson.cn> Acked-by:
Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-12-gaosong@loongson.cn> Message-Id: <20230822071959.35620-6-philmd@linaro.org>
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Song Gao authored
Allow virt machine to be used with la132 instead of la464. Co-authored-by:
Jiajie Chen <c@jia.je> Signed-off-by:
Song Gao <gaosong@loongson.cn> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-11-gaosong@loongson.cn> Message-Id: <20230822071959.35620-5-philmd@linaro.org>
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Jiajie Chen authored
Add LoongArch32 cpu la132. Due to lack of public documentation of la132, it is currently a synthetic LoongArch32 cpu model. Details need to be added in the future. Signed-off-by:
Jiajie Chen <c@jia.je> Signed-off-by:
Song Gao <gaosong@loongson.cn> Acked-by:
Richard Henderson <richard.henderson@linaro.org> Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-10-gaosong@loongson.cn> Message-Id: <20230822071959.35620-4-philmd@linaro.org>
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Song Gao authored
The la32 instructions listed in Table 2 at https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#overview-of-basic-integer-instructions Co-authored-by:
Jiajie Chen <c@jia.je> Signed-off-by:
Song Gao <gaosong@loongson.cn> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-9-gaosong@loongson.cn> Message-Id: <20230822071959.35620-3-philmd@linaro.org>
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Song Gao authored
The default check parmeter is ALL. Suggested-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Song Gao <gaosong@loongson.cn> Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-8-gaosong@loongson.cn> Message-Id: <20230822071959.35620-2-philmd@linaro.org>
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Jiajie Chen authored
In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low 32 bit result to 64 bits. Signed-off-by:
Jiajie Chen <c@jia.je> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Song Gao <gaosong@loongson.cn> Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-7-gaosong@loongson.cn> Message-Id: <20230822071959.35620-1-philmd@linaro.org>
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Jiajie Chen authored
When running in VA32 mode(!LA64 or VA32L[1-3] matching PLV), virtual address is truncated to 32 bits before address mapping. Signed-off-by:
Jiajie Chen <c@jia.je> Co-authored-by:
Richard Henderson <richard.henderson@linaro.org> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Song Gao <gaosong@loongson.cn> Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn> Message-Id: <20230822071405.35386-10-philmd@linaro.org>
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Jiajie Chen authored
Signed-off-by:
Jiajie Chen <c@jia.je> Co-authored-by:
Richard Henderson <richard.henderson@linaro.org> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Song Gao <gaosong@loongson.cn> Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230822071405.35386-9-philmd@linaro.org>
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Jiajie Chen authored
Signed-off-by:
Jiajie Chen <c@jia.je> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Song Gao <gaosong@loongson.cn> Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-7-gaosong@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230822071405.35386-8-philmd@linaro.org>
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Jiajie Chen authored
Signed-off-by:
Jiajie Chen <c@jia.je> Co-authored-by:
Richard Henderson <richard.henderson@linaro.org> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Song Gao <gaosong@loongson.cn> Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230822071405.35386-7-philmd@linaro.org>
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Jiajie Chen authored
Signed-off-by:
Jiajie Chen <c@jia.je> Co-authored-by:
Richard Henderson <richard.henderson@linaro.org> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Song Gao <gaosong@loongson.cn> Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230822071405.35386-6-philmd@linaro.org>
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Jiajie Chen authored
Add LA64 and VA32(32-bit Virtual Address) to DisasContext to allow the translator to reject doubleword instructions in LA32 mode for example. Signed-off-by:
Jiajie Chen <c@jia.je> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Song Gao <gaosong@loongson.cn> Message-ID: <20230822032724.1353391-5-gaosong@loongson.cn> Message-Id: <20230822071405.35386-5-philmd@linaro.org>
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Jiajie Chen authored
VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32. Signed-off-by:
Jiajie Chen <c@jia.je> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Song Gao <gaosong@loongson.cn> Message-ID: <20230822032724.1353391-4-gaosong@loongson.cn> Message-Id: <20230822071405.35386-4-philmd@linaro.org>
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Jiajie Chen authored
LA32 uses a different encoding for CSR.DMW and a new direct mapping mechanism. Signed-off-by:
Jiajie Chen <c@jia.je> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Song Gao <gaosong@loongson.cn> Message-ID: <20230822032724.1353391-3-gaosong@loongson.cn> Message-Id: <20230822071405.35386-3-philmd@linaro.org>
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Jiajie Chen authored
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to zero in LoongArch32. Signed-off-by:
Jiajie Chen <c@jia.je> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Song Gao <gaosong@loongson.cn> Message-ID: <20230822032724.1353391-2-gaosong@loongson.cn> Message-Id: <20230822071405.35386-2-philmd@linaro.org>
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Jiajie Chen authored
GPRs and PC are 32-bit wide in loongarch32 mode. Signed-off-by:
Jiajie Chen <c@jia.je> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Song Gao <gaosong@loongson.cn> Message-ID: <20230817093121.1053890-4-gaosong@loongson.cn> [PMD: Rebased, set gdb_num_core_regs] Signed-off-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230821125959.28666-9-philmd@linaro.org>
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Jiajie Chen authored
Add object class stub for future loongarch32 cpus. Signed-off-by:
Jiajie Chen <c@jia.je> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Song Gao <gaosong@loongson.cn> Message-ID: <20230817093121.1053890-3-gaosong@loongson.cn> [Rebased on TYPE_LOONGARCH64_CPU introduction] Signed-off-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230821125959.28666-8-philmd@linaro.org>
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Jiajie Chen authored
Add is_la64 function to check if the current cpucfg[1].arch equals to 2(LA64). Signed-off-by:
Jiajie Chen <c@jia.je> Co-authored-by:
Richard Henderson <richard.henderson@linaro.org> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Song Gao <gaosong@loongson.cn> Message-ID: <20230817093121.1053890-2-gaosong@loongson.cn> Signed-off-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230821125959.28666-7-philmd@linaro.org>
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Philippe Mathieu-Daudé authored
Extract loongarch64 specific code from loongarch_cpu_class_init() to a new loongarch64_cpu_class_init(). In preparation of supporting loongarch32 cores, rename these functions using the '64' suffix. Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Signed-off-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230821125959.28666-6-philmd@linaro.org> Signed-off-by:
Song Gao <gaosong@loongson.cn>
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Philippe Mathieu-Daudé authored
In preparation of introducing TYPE_LOONGARCH32_CPU, introduce an abstract TYPE_LOONGARCH64_CPU. Signed-off-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230821125959.28666-5-philmd@linaro.org> Signed-off-by:
Song Gao <gaosong@loongson.cn>
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