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  1. Aug 22, 2023
  3. Aug 16, 2023
  5. Aug 15, 2023
    • Richard Henderson's avatar
      Merge tag 'pull-tcg-20230814' of https://gitlab.com/rth7680/qemu into staging · 408af44d
      Richard Henderson authored 
      tcg/i386: Output %gs prefix in tcg_out_vex_opc

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* tag 'pull-tcg-20230814' of https://gitlab.com/rth7680/qemu

:
  tcg/i386: Output %gs prefix in tcg_out_vex_opc

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      408af44d
  7. Aug 12, 2023
  9. Aug 11, 2023
    • Richard Henderson's avatar
      Merge tag 'pull-riscv-to-apply-20230811-3' of https://github.com/alistair23/qemu into staging · bb5f142c
      Richard Henderson authored 
      Sixth RISC-V PR for 8.1

This is a last minute PR for RISC-V.

The main goal is to fix
https://gitlab.com/qemu-project/qemu/-/issues/1823
which is a regression that means the aclint option
cannot be enabled.

While we are here we also fixup KVM issue.

 * KVM: fix mvendorid size
 * Fixup aclint check

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* tag 'pull-riscv-to-apply-20230811-3' of https://github.com/alistair23/qemu

:
  hw/riscv/virt.c: change 'aclint' TCG check
  target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids()

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      bb5f142c
    • Daniel Henrique Barboza's avatar
      hw/riscv/virt.c: change 'aclint' TCG check · b274c238
      Daniel Henrique Barboza authored 
      The 'aclint' property is being conditioned with tcg acceleration in
virt_machine_class_init(). But acceleration code starts later than the
class init of the board, meaning that tcg_enabled() will be always be
false during class_init(), and the option is never being declared even
when declaring TCG accel:

$ ./build/qemu-system-riscv64 -M virt,accel=tcg,aclint=on
qemu-system-riscv64: Property 'virt-machine.aclint' not found

Fix it by moving the check from class_init() to machine_init(). Tune the
description to mention that the option is TCG only.

Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Fixes: c0716c81 ("hw/riscv/virt: Restrict ACLINT to TCG")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1823


Signed-off-by: default avatarDaniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: default avatarPhilippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230811160224.440697-2-dbarboza@ventanamicro.com>
Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
      b274c238
    • Daniel Henrique Barboza's avatar
      target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids() · 136cb9cc
      Daniel Henrique Barboza authored 
      
cpu->cfg.mvendorid is a 32 bit field and kvm_set_one_reg() always write
a target_ulong val, i.e. a 64 bit field in a 64 bit host.

Given that we're passing a pointer to the mvendorid field, the reg is
reading 64 bits starting from mvendorid and going 32 bits in the next
field, marchid. Here's an example:

$ ./qemu-system-riscv64 -machine virt,accel=kvm -m 2G -smp 1 \
   -cpu rv64,marchid=0xab,mvendorid=0xcd,mimpid=0xef(...)

(inside the guest)
 # cat /proc/cpuinfo
processor	: 0
hart		: 0
isa		: rv64imafdc_zicbom_zicboz_zihintpause_zbb_sstc
mmu		: sv57
mvendorid	: 0xab000000cd
marchid		: 0xab
mimpid		: 0xef

'mvendorid' was written as a combination of 0xab (the value from the
adjacent field, marchid) and its intended value 0xcd.

Fix it by assigning cpu->cfg.mvendorid to a target_ulong var 'reg' and
use it as input for kvm_set_one_reg(). Here's the result with this patch
applied and using the same QEMU command line:

 # cat /proc/cpuinfo
processor	: 0
hart		: 0
isa		: rv64imafdc_zicbom_zicboz_zihintpause_zbb_sstc
mmu		: sv57
mvendorid	: 0xcd
marchid		: 0xab
mimpid		: 0xef

This bug affects only the generic (rv64) CPUs when running with KVM in a
64 bit env since the 'host' CPU does not allow the machine IDs to be
changed via command line.

Fixes: 1fb5a622 ("target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs")
Signed-off-by: default avatarDaniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Message-ID: <20230802180058.281385-1-dbarboza@ventanamicro.com>
Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
      136cb9cc
    • Richard Henderson's avatar
      Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging · 44e13cb4
      Richard Henderson authored 
      
pci: last minute bugfixes

two fixes that seem very safe and important enough to sneak
in before the release.

Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>

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# gpg: Signature made Fri 11 Aug 2023 09:16:50 AM PDT
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# gpg:                issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [undefined]
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu

:
  pci: Fix the update of interrupt disable bit in PCI_COMMAND register
  hw/pci-host: Allow extended config space access for Designware PCIe host

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      44e13cb4
    • Guoyi Tu's avatar
      pci: Fix the update of interrupt disable bit in PCI_COMMAND register · 0f936247
      Guoyi Tu authored 
      
The PCI_COMMAND register is located at offset 4 within
the PCI configuration space and occupies 2 bytes. The
interrupt disable bit is at the 10th bit, which corresponds
to the byte at offset 5 in the PCI configuration space.

In our testing environment, the guest driver may directly
updates the byte at offset 5 in the PCI configuration space.
The backtrace looks like as following:
    at hw/pci/pci.c:1442
    at hw/virtio/virtio-pci.c:605
    val=5, len=1) at hw/pci/pci_host.c:81

In this situation, the range_covers_byte function called
by the pci_default_write_config function will return false,
resulting in the inability to handle the interrupt disable
update event.

To fix this issue, we can use the ranges_overlap function
instead of range_covers_byte to determine whether the interrupt
bit has been updated.

Signed-off-by: default avatarGuoyi Tu <tugy@chinatelecom.cn>
Signed-off-by: default avataryuanminghao <yuanmh12@chinatelecom.cn>
Message-Id: <ce2d0437-8faa-4d61-b536-4668f645a959@chinatelecom.cn>
Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
Fixes: b6981cb5 ("pci: interrupt disable bit support")
      0f936247
    • Jason Chien's avatar
      hw/pci-host: Allow extended config space access for Designware PCIe host · 3d449bc6
      Jason Chien authored 
      
In pcie_bus_realize(), a root bus is realized as a PCIe bus and a non-root
bus is realized as a PCIe bus if its parent bus is a PCIe bus. However,
the child bus "dw-pcie" is realized before the parent bus "pcie" which is
the root PCIe bus. Thus, the extended configuration space is not accessible
on "dw-pcie". The issue can be resolved by adding the
PCI_BUS_EXTENDED_CONFIG_SPACE flag to "pcie" before "dw-pcie" is realized.

Signed-off-by: default avatarJason Chien <jason.chien@sifive.com>
Message-Id: <20230809102257.25121-1-jason.chien@sifive.com>
Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
Reviewed-by: default avatarFrank Chang <frank.chang@sifive.com>
Signed-off-by: default avatarJason Chien &amp;lt;&lt;a href="mailto:jason.chien@sifive.com" <target="_blank"&gt;jason.chien@sifive.com&lt;/a&gt;&amp;gt;&lt;br>
      3d449bc6
  11. Aug 10, 2023
  13. Aug 09, 2023
  15. Aug 08, 2023