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  1. Sep 26, 2022
    • Andrew Burgess's avatar
      target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml · 94452ac4
      Andrew Burgess authored
      
      While testing some changes to GDB's handling for the RISC-V registers
      fcsr, fflags, and frm, I spotted that QEMU includes these registers
      twice in the target description it sends to GDB, once in the fpu
      feature, and once in the csr feature.
      
      Right now things basically work OK, QEMU maps these registers onto two
      different register numbers, e.g. fcsr maps to both 68 and 73, and GDB
      can use either of these to access the register.
      
      However, GDB's target descriptions don't really work this way, each
      register should appear just once in a target description, mapping the
      register name onto the number GDB should use when accessing the
      register on the target.  Duplicate register names actually result in
      duplicate registers on the GDB side, however, as the registers have
      the same name, the user can only access one of these registers.
      
      Currently GDB has a hack in place, specifically for RISC-V, to spot
      the duplicate copies of these three registers, and hide them from the
      user, ensuring the user only ever sees a single copy of each.
      
      In this commit I propose fixing this issue on the QEMU side, and in
      the process, simplify the fpu register handling a little.
      
      I think we should, remove fflags, frm, and fcsr from the two (32-bit
      and 64-bit) fpu feature xml files.  These files will only contain the
      32 core floating point register f0 to f31.  The fflags, frm, and fcsr
      registers will continue to be advertised in the csr feature as they
      currently are.
      
      With that change made, I will simplify riscv_gdb_get_fpu and
      riscv_gdb_set_fpu, removing the extra handling for the 3 status
      registers.
      
      Signed-off-by: default avatarAndrew Burgess <aburgess@redhat.com>
      Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
      Message-Id: <0fbf2a5b12e3210ff3867d5cf7022b3f3462c9c8.1661934573.git.aburgess@redhat.com>
      Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
      94452ac4
    • Weiwei Li's avatar
      target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h} · a4128294
      Weiwei Li authored
      
      - modify check for mcounteren to work in all less-privilege mode
      - modify check for scounteren to work only when S mode is enabled
      - distinguish the exception type raised by check for scounteren between U
      and VU mode
      
      Signed-off-by: default avatarWeiwei Li <liweiwei@iscas.ac.cn>
      Signed-off-by: default avatarJunqiang Wang <wangjunqiang@iscas.ac.cn>
      Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
      Message-Id: <20220817083756.12471-1-liweiwei@iscas.ac.cn>
      Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
      a4128294
    • Rahul Pathak's avatar
      target/riscv: Remove sideleg and sedeleg · 513eb437
      Rahul Pathak authored
      sideleg and sedeleg csrs are not part of riscv isa spec
      anymore, these csrs were part of N extension which
      is removed from the riscv isa specification.
      
      These commits removed all traces of these csrs from
      riscv spec (https://github.com/riscv/riscv-isa-manual
      
      ) -
      
      commit f8d27f805b65 ("Remove or downgrade more references to N extension (#674)")
      commit b6cade07034d ("Remove N extension chapter for now")
      
      Signed-off-by: default avatarRahul Pathak <rpathak@ventanamicro.com>
      Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
      Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
      Message-Id: <20220824145255.400040-1-rpathak@ventanamicro.com>
      Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
      513eb437
    • Alex Bennée's avatar
      docs/system: clean up code escape for riscv virt platform · 0c2d4671
      Alex Bennée authored
      
      The example code is rendered slightly mangled due to missing code
      block. Properly escape the code block and add shell prompt and qemu to
      fit in with the other examples on the page.
      
      Signed-off-by: default avatarAlex Bennée <alex.bennee@linaro.org>
      Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
      Message-Id: <20220905163939.1599368-1-alex.bennee@linaro.org>
      Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
      0c2d4671
    • Wilfred Mallawa's avatar
      hw/ssi: ibex_spi: update reg addr · 7a426f83
      Wilfred Mallawa authored
      Updates the `EVENT_ENABLE` register to offset `0x34` as per
      OpenTitan spec [1].
      
      [1] https://docs.opentitan.org/hw/ip/spi_host/doc/#Reg_event_enable
      
      
      
      Signed-off-by: default avatarWilfred Mallawa <wilfred.mallawa@wdc.com>
      Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
      Message-Id: <20220823061201.132342-5-wilfred.mallawa@opensource.wdc.com>
      Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
      7a426f83
    • Wilfred Mallawa's avatar
      hw/ssi: ibex_spi: fixup typos in ibex_spi_host · a4455863
      Wilfred Mallawa authored
      
      This patch fixes up minor typos in ibex_spi_host
      
      Signed-off-by: default avatarWilfred Mallawa <wilfred.mallawa@wdc.com>
      Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
      Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
      Message-Id: <20220823061201.132342-2-wilfred.mallawa@opensource.wdc.com>
      Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
      a4455863
    • Stefan Hajnoczi's avatar
      Merge tag 'pull-target-arm-20220922' of... · 99d6b11b
      Stefan Hajnoczi authored
      Merge tag 'pull-target-arm-20220922' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
      
      target-arm queue:
       * hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic
       * Fix alignment for Neon VLD4.32
       * Refactoring of page-table-walk code
       * hw/acpi: Add ospm_status hook implementation for acpi-ged
       * hw/net/lan9118: Signal TSFL_INT flag when TX FIFO reaches specified level
       * chardev/baum: avoid variable-length arrays
       * io/channel-websock: avoid variable-length arrays
       * hw/net/e1000e_core: Use definition to avoid dynamic stack allocation
       * hw/ppc/pnv: Avoid dynamic stack allocation
       * hw/intc/xics: Avoid dynamic stack allocation
       * hw/i386/multiboot: Avoid dynamic stack allocation
       * hw/usb/hcd-ohci: Use definition to avoid dynamic stack allocation
       * ui/curses: Avoid dynamic stack allocation
       * tests/unit/test-vmstate: Avoid dynamic stack allocation
       * configure: fix various shellcheck-spotted issues and nits
      
      # -----BEGIN PGP SIGNATURE-----
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      # =hec8
      # -----END PGP SIGNATURE-----
      # gpg: Signature made Thu 22 Sep 2022 12:34:15 EDT
      # gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
      # gpg:                issuer "peter.maydell@linaro.org"
      # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
      # gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
      # gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
      # gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
      # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE
      
      * tag 'pull-target-arm-20220922' of https://git.linaro.org/people/pmaydell/qemu-arm
      
      : (39 commits)
        configure: Avoid use of 'local' as it is non-POSIX
        configure: Check mkdir result directly, not via $?
        configure: Remove use of backtick `...` syntax
        configure: Add './' on front of glob of */config-devices.mak.d
        configure: Add missing quoting for some easy cases
        configure: Remove unused meson_args variable
        configure: Remove unused python_version variable
        tests/unit/test-vmstate: Avoid dynamic stack allocation
        ui/curses: Avoid dynamic stack allocation
        hw/usb/hcd-ohci: Use definition to avoid dynamic stack allocation
        hw/i386/multiboot: Avoid dynamic stack allocation
        hw/intc/xics: Avoid dynamic stack allocation
        hw/ppc/pnv: Avoid dynamic stack allocation
        hw/net/e1000e_core: Use definition to avoid dynamic stack allocation
        io/channel-websock: Replace strlen(const_str) by sizeof(const_str) - 1
        chardev/baum: Avoid dynamic stack allocation
        chardev/baum: Use definitions to avoid dynamic stack allocation
        chardev/baum: Replace magic values by X_MAX / Y_MAX definitions
        hw/net/lan9118: Signal TSFL_INT flag when TX FIFO reaches specified level
        hw/acpi: Add ospm_status hook implementation for acpi-ged
        ...
      
      Signed-off-by: default avatarStefan Hajnoczi <stefanha@redhat.com>
      99d6b11b
  2. Sep 22, 2022
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