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    • Peter Maydell's avatar
      hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registers · a68fc9db
      Peter Maydell authored
      
      The hypervisor can deliver (virtual) LPIs to a guest by setting up a
      list register to have an intid which is an LPI.  The GIC has to treat
      these a little differently to standard interrupt IDs, because LPIs
      have no Active state, and so the guest will only EOI them, it will
      not also deactivate them.  So icv_eoir_write() must do two things:
      
       * if the LPI ID is not in any list register, we drop the
         priority but do not increment the EOI count
       * if the LPI ID is in a list register, we immediately deactivate
         it, regardless of the split-drop-and-deactivate control
      
      This can be seen in the VirtualWriteEOIR0() and VirtualWriteEOIR1()
      pseudocode in the GICv3 architecture specification.
      
      Without this fix, potentially a hypervisor guest might stall because
      LPIs get stuck in a bogus Active+Pending state.
      
      Cc: qemu-stable@nongnu.org
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Tested-by: default avatarMiguel Luis <miguel.luis@oracle.com>
      (cherry picked from commit 82a65e3188abebb509510b391726711606aca642)
      Signed-off-by: default avatarMichael Tokarev <mjt@tls.msk.ru>
      a68fc9db
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