- Oct 30, 2021
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BALATON Zoltan authored
The hw_error function calls abort and is not meant to be used by devices. Use qemu_log_mask instead to log and ignore invalid accesses. Also fix format strings to allow dropping type casts of hwaddr and use __func__ instead of hard coding function name in the message which were wrong in two cases. Signed-off-by:
BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <f818dc3dd2ac8c3b3d53067f316a716d7f9683d8.1635541329.git.balaton@eik.bme.hu> Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org>
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BALATON Zoltan authored
The timer unit only has registers that fit in a region 0x30 bytes long. No need to have the timer region larger than that. Signed-off-by:
BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <b1cd196cf1395a602c7a08a4f858e69e50c446a1.1635550060.git.balaton@eik.bme.hu> Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org>
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BALATON Zoltan authored
It's more readable to keep things on one line if it fits the length limit. Signed-off-by:
BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <97bc2a38991f33fd0c8cc2e4d0a3a29b20c47d1f.1635541329.git.balaton@eik.bme.hu> Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org>
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BALATON Zoltan authored
According to coding style types should be camel case, also remove unneded casts from void *. Signed-off-by:
BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <d9a9d160c1153a583397e366ab06477f5a31c507.1635541329.git.balaton@eik.bme.hu> Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org>
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BALATON Zoltan authored
Signed-off-by:
BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-Id: <b776043e811ab3caf200515e1350bdcccd1cc47b.1635541329.git.balaton@eik.bme.hu> [PMD: Fixed format strings for 32-bit hosts] Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org>
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BALATON Zoltan authored
Signed-off-by:
BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <a84405db64ef81bff1a16526da290cc68f1444db.1635541329.git.balaton@eik.bme.hu> Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org>
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BALATON Zoltan authored
Signed-off-by:
BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <6cb1bcf24572ad8465c20b64fec81157f34bcbe9.1635541329.git.balaton@eik.bme.hu> Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org>
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BALATON Zoltan authored
Signed-off-by:
BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <b53a8cbcf57207fbd6408db1007b3e82008d60f7.1635541329.git.balaton@eik.bme.hu> Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org>
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BALATON Zoltan authored
Signed-off-by:
BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <91698c54fa493a4cfe93546211206439787d4b78.1635541329.git.balaton@eik.bme.hu> Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org>
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BALATON Zoltan authored
Signed-off-by:
BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <3f192c699f4e5949ec0fcc436e5610f50afe2dbf.1635541329.git.balaton@eik.bme.hu> Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org>
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- Sep 20, 2021
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Alistair Francis authored
This is the initial commit of the SiFive PWM timer. This is used by guest software as a timer and is included in the SiFive FU540 SoC. Signed-off-by:
Justin Restivo <jrestivo@draper.com> Signed-off-by:
Alexandra Clifford <aclifford@draper.com> Signed-off-by:
Amanda Strnad <astrnad@draper.com> Signed-off-by:
Alistair Francis <alistair.francis@wdc.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> Message-id: 9f70a210acbfaf0e1ea6ad311ab892ac69134d8b.1631159656.git.alistair.francis@wdc.com
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Alistair Francis authored
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the timer MIP bits. Signed-off-by:
Alistair Francis <alistair.francis@wdc.com> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 84d5b1d5783d2e79eee69a2f7ac480cc0c070db3.1630301632.git.alistair.francis@wdc.com
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- Sep 01, 2021
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Peter Maydell authored
All the devices that used to use system_clock_scale have now been converted to use Clock inputs instead, so the global is no longer needed; remove it and all the code that sets it. Signed-off-by:
Peter Maydell <peter.maydell@linaro.org> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com> Message-id: 20210812093356.1946-26-peter.maydell@linaro.org
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Peter Maydell authored
The stellaris-gptm timer currently uses system_clock_scale for one of its timer modes where the timer runs at the CPU clock rate. Make it use a Clock input instead. We don't try to make the timer handle changes in the clock frequency while the downcounter is running. This is not a change in behaviour from the previous system_clock_scale implementation -- we will pick up the new frequency only when the downcounter hits zero. Handling dynamic clock changes when the counter is running would require state that the current gptm implementation doesn't have. Signed-off-by:
Peter Maydell <peter.maydell@linaro.org> Reviewed-by:
Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-25-peter.maydell@linaro.org
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Peter Maydell authored
The implementation of the Stellaris general purpose timer module device stellaris-gptm is currently in the same source file as the board model. Split it out into its own source file in hw/timer. Apart from the new file comment headers and the Kconfig and meson.build changes, this is just code movement. Signed-off-by:
Peter Maydell <peter.maydell@linaro.org> Reviewed-by:
Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-24-peter.maydell@linaro.org
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Peter Maydell authored
Now that all users of the systick devices wire up the clock inputs, use those instead of the system_clock_scale and the hardwired 1MHz value for the reference clock. This will fix various board models where we were incorrectly providing a 1MHz reference clock instead of some other value or instead of providing no reference clock at all. Signed-off-by:
Peter Maydell <peter.maydell@linaro.org> Reviewed-by:
Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-22-peter.maydell@linaro.org
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Peter Maydell authored
The v7M systick timer can be programmed to run from either of two clocks: * an "external reference clock" (when SYST_CSR.CLKSOURCE == 0) * the main CPU clock (when SYST_CSR.CLKSOURCE == 1) Our implementation currently hardwires the external reference clock to be 1MHz, and allows boards to set the main CPU clock frequency via the global 'system_clock_scale'. (Most boards set that to a constant value; the Stellaris boards allow the guest to reprogram it via the board-specific RCC registers). As the first step in converting this to use the Clock infrastructure, add input clocks to the systick device for the reference clock and the CPU clock. The device implementation ignores them; once we have made all the users of the device correctly wire up the new Clocks we will switch the implementation to use them and ignore the old system_clock_scale. This is a migration compat break for all M-profile boards, because of the addition of the new clock objects to the vmstate struct. Signed-off-by:
Peter Maydell <peter.maydell@linaro.org> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com> Reviewed-by:
Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-6-peter.maydell@linaro.org
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- Jun 24, 2021
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Alistair Francis authored
Add support for the Ibex timer. This is used with the RISC-V mtime/mtimecmp similar to the SiFive CLINT. We currently don't support changing the prescale or the timervalue. Signed-off-by:
Alistair Francis <alistair.francis@wdc.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> Message-id: 716fdea2244515ce86a2c46fe69467d013c03147.1624001156.git.alistair.francis@wdc.com
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- Jun 02, 2021
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Stefano Garzarella authored
Commit e50caf4a ("tracing: convert documentation to rST") converted docs/devel/tracing.txt to docs/devel/tracing.rst. We still have several references to the old file, so let's fix them with the following command: sed -i s/tracing.txt/tracing.rst/ $(git grep -l docs/devel/tracing.txt) Signed-off-by:
Stefano Garzarella <sgarzare@redhat.com> Reviewed-by:
Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210517151702.109066-2-sgarzare@redhat.com> Signed-off-by:
Thomas Huth <thuth@redhat.com>
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- May 13, 2021
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Philippe Mathieu-Daudé authored
TYPE_ETRAX_FS_TIMER is a sysbus device, so its DeviceClass::reset() handler is called automatically when its qbus parent is reset (we don't need to register it manually). Convert the generic reset to a enter/hold resettable ones, and remove the qemu_register_reset() call. Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <20210502163931.552675-2-f4bug@amsat.org> Signed-off-by:
Laurent Vivier <laurent@vivier.eu>
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- May 12, 2021
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Markus Armbruster authored
Target unicore32 was deprecated in commit 8e4ff4a8, v5.2.0. See there for rationale. Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Signed-off-by:
Markus Armbruster <armbru@redhat.com> Message-Id: <20210503084034.3804963-3-armbru@redhat.com> Acked-by:
Thomas Huth <thuth@redhat.com>
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Markus Armbruster authored
Target lm32 was deprecated in commit d8498005, v5.2.0. See there for rationale. Some of its code lives on in device models derived from milkymist ones: hw/char/digic-uart.c and hw/display/bcm2835_fb.c. Cc: Michael Walle <michael@walle.cc> Signed-off-by:
Markus Armbruster <armbru@redhat.com> Message-Id: <20210503084034.3804963-2-armbru@redhat.com> Acked-by:
Michael Walle <michael@walle.cc> [Trivial conflicts resolved, reST markup fixed]
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- May 02, 2021
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Thomas Huth authored
Many files include hw/irq.h without needing it. Remove the superfluous include statements. Signed-off-by:
Thomas Huth <thuth@redhat.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210327050236.2232347-1-thuth@redhat.com> Signed-off-by:
Laurent Vivier <laurent@vivier.eu>
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Thomas Huth authored
Many files include hw/sysbus.h without needing it. Remove the superfluous include statements. Signed-off-by:
Thomas Huth <thuth@redhat.com> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210327082804.2259480-1-thuth@redhat.com> Signed-off-by:
Laurent Vivier <laurent@vivier.eu>
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- Mar 30, 2021
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Peter Maydell authored
In commit 81b3ddaf we fixed a use of uninitialized data in read_tcnt(). However this change wasn't enough to placate Coverity, which is not smart enough to see that if we read a 2 bit field and then handle cases 0, 1, 2 and 3 then there cannot be a flow of execution through the switch default. Add explicit default cases which assert that they can't be reached, which should help silence Coverity. Signed-off-by:
Peter Maydell <peter.maydell@linaro.org> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210319162458.13760-1-peter.maydell@linaro.org
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- Mar 19, 2021
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Markus Armbruster authored
Several QOM type names contain ',': ARM,bitband-memory etraxfs,pic etraxfs,serial etraxfs,timer fsl,imx25 fsl,imx31 fsl,imx6 fsl,imx6ul fsl,imx7 grlib,ahbpnp grlib,apbpnp grlib,apbuart grlib,gptimer grlib,irqmp qemu,register SUNW,bpp SUNW,CS4231 SUNW,DBRI SUNW,DBRI.prom SUNW,fdtwo SUNW,sx SUNW,tcx xilinx,zynq_slcr xlnx,zynqmp xlnx,zynqmp-pmu-soc xlnx,zynq-xadc These are all device types. They can't be plugged with -device / device_add, except for xlnx,zynqmp-pmu-soc, and I doubt that one actually works. They *can* be used with -device / device_add to request help. Usability is poor, though: you have to double the comma, like this: $ qemu-system-x86_64 -device SUNW,,fdtwo,help Trap for the unwary. The fact that this was broken in device-introspect-test for more than six years until commit e27bd498 fixed it demonstrates that "the unwary" includes seasoned developers. One QOM type name contains ' ': "ICH9 SMB". Because having to remember just one way to quote would be too easy. Rename the "SUNW,FOO types to "sun-FOO". Summarily replace ',' and ' ' by '-' in the other type names. Signed-off-by:
Markus Armbruster <armbru@redhat.com> Message-Id: <20210304140229.575481-2-armbru@redhat.com> Reviewed-by:
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by:
Paolo Bonzini <pbonzini@redhat.com>
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- Mar 16, 2021
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Pavel Dovgalyuk authored
QEMU timer of channel 0 in i8254 is used to raise irq at the specified moment of time. This irq can be disabled with irq_disabled flag. But when vmstate of the pit is loaded, timer may be rearmed despite the disabled interrupts. This patch adds irq_disabled flag check to fix that. Signed-off-by:
Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Message-Id: <161537170060.6654.9430112746749476215.stgit@pasha-ThinkPad-X280> Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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- Mar 12, 2021
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Philippe Mathieu-Daudé authored
If the SSECounter link is absent, we set an error message in sse_timer_realize() but forgot to propagate this error. Add the missing 'return'. Fixes: CID 1450755 (Null pointer dereferences) Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210312001845.1562670-1-f4bug@amsat.org Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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- Mar 10, 2021
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Peter Maydell authored
The read_tcnt() function calculates the TCNT register values for the two channels of the timer module; it sets these up in the local tcnt[] array, and eventually returns either one or both of them, depending on whether the access is 8 or 16 bits. However, not all of the code paths through this function set both elements of this array: if the guest has programmed the TCCR.CSS register fields to values which are either documented as not to be used or which QEMU does not implement, then the function will return uninitialized data. (This was spotted by Coverity.) Add the missing CSS cases to this code, so that we return a consistent value instead of uninitialized data, and so the code structure indicates what's happening. Fixes: CID 1429976 Signed-off-by:
Peter Maydell <peter.maydell@linaro.org> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210219223241.16344-3-peter.maydell@linaro.org
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Peter Maydell authored
The #defines INTERNAL and CASCADING represent different possible values for the TCCR.CSS register field; prefix them with CSS_ to make this more obvious, before we add more defines to represent the other possible values of the field in the next commit. Signed-off-by:
Peter Maydell <peter.maydell@linaro.org> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210219223241.16344-2-peter.maydell@linaro.org
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- Mar 09, 2021
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Philippe Mathieu-Daudé authored
We want to be able to use the 'LM32' config for architecture specific features. As CONFIG_LM32 is only used to select peripherals, rename it CONFIG_LM32_DEVICES. Reviewed-by:
Alex Bennée <alex.bennee@linaro.org> Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210221225626.2589247-3-f4bug@amsat.org> Signed-off-by:
Laurent Vivier <laurent@vivier.eu>
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- Mar 08, 2021
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Peter Maydell authored
The SSE-300 includes some timers which are a different kind to those in the SSE-200. Model them. These timers are documented in the SSE-123 Example Subsystem Technical Reference Manual: https://developer.arm.com/documentation/101370/latest/ Signed-off-by:
Peter Maydell <peter.maydell@linaro.org> Tested-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-13-peter.maydell@linaro.org
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Peter Maydell authored
The SSE-300 includes a counter module; implement a model of it. This counter is documented in the SSE-123 Example Subsystem Technical Reference Manual: https://developer.arm.com/documentation/101370/latest/ Signed-off-by:
Peter Maydell <peter.maydell@linaro.org> Tested-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-12-peter.maydell@linaro.org
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Peter Maydell authored
Use the new clock_ns_to_ticks() function in npcm7xx_timer where appropriate. Signed-off-by:
Peter Maydell <peter.maydell@linaro.org> Reviewed-by:
Luc Michel <luc@lmichel.fr> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Hao Wu <wuhaotsh@google.com> Tested-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210219144617.4782-5-peter.maydell@linaro.org
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Peter Maydell authored
The Clock framework allows users to specify a callback which is called after the clock's period has been updated. Some users need to also have a callback which is called before the clock period is updated. As the first step in adding support for notifying Clock users on pre-update events, add an argument to the ClockCallback to specify what event is being notified, and add an argument to the various functions for registering a callback to specify which events are of interest to that callback. Note that the documentation update renders correct the previously incorrect claim in 'Adding a new clock' that callbacks "will be explained in a following section". Signed-off-by:
Peter Maydell <peter.maydell@linaro.org> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Luc Michel <luc@lmichel.fr> Tested-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-2-peter.maydell@linaro.org
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- Mar 06, 2021
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Philippe Mathieu-Daudé authored
We want to be able to use the 'SH4' config for architecture specific features. Add more fine-grained selection by adding a CONFIG_SH_TIMER selector for the SH4 timer control unit. Add the missing MAINTAINERS entries. Suggested-by:
Peter Maydell <peter.maydell@linaro.org> Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Richard Henderson <richard.henderson@linaro.org> Acked-by:
Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210222141514.2646278-6-f4bug@amsat.org>
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- Feb 11, 2021
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Peter Maydell authored
Update infocenter.arm.com URLs for various pieces of Arm documentation to the new developer.arm.com equivalents. (There is a redirection in place from the old URLs, but we might as well update our comments in case the redirect ever disappears in future.) This patch covers all the URLs which are not MPS2/SSE-200/IoTKit related (those are dealt with in a different patch). Signed-off-by:
Peter Maydell <peter.maydell@linaro.org> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210205171456.19939-1-peter.maydell@linaro.org
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- Jan 29, 2021
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Peter Maydell authored
Now no users are setting the frq properties on the CMSDK timer, dualtimer, watchdog or ARMSSE SoC devices, we can remove the properties and the struct fields that back them. Signed-off-by:
Peter Maydell <peter.maydell@linaro.org> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Luc Michel <luc@lmichel.fr> Tested-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210128114145.20536-25-peter.maydell@linaro.org Message-id: 20210121190622.22000-25-peter.maydell@linaro.org
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Peter Maydell authored
Switch the CMSDK APB dualtimer device over to using its Clock input; the pclk-frq property is now ignored. Signed-off-by:
Peter Maydell <peter.maydell@linaro.org> Reviewed-by:
Luc Michel <luc@lmichel.fr> Tested-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210128114145.20536-20-peter.maydell@linaro.org Message-id: 20210121190622.22000-20-peter.maydell@linaro.org Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org>
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Peter Maydell authored
Switch the CMSDK APB timer device over to using its Clock input; the pclk-frq property is now ignored. Signed-off-by:
Peter Maydell <peter.maydell@linaro.org> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
Luc Michel <luc@lmichel.fr> Tested-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210128114145.20536-19-peter.maydell@linaro.org Message-id: 20210121190622.22000-19-peter.maydell@linaro.org
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