Skip to content
Snippets Groups Projects
  1. Nov 21, 2017
    • Peter Maydell's avatar
      accel/tcg: Handle atomic accesses to notdirty memory correctly · 34d49937
      Peter Maydell authored
      
      To do a write to memory that is marked as notdirty, we need
      to invalidate any TBs we have cached for that memory, and
      update the cpu physical memory dirty flags for VGA and migration.
      The slowpath code in notdirty_mem_write() does all this correctly,
      but the new atomic handling code in atomic_mmu_lookup() doesn't
      do anything at all, it just clears the dirty bit in the TLB.
      
      The effect of this bug is that if the first write to a notdirty
      page for which we have cached TBs is by a guest atomic access,
      we fail to invalidate the TBs and subsequently will execute
      incorrect code. This can be seen by trying to run 'javac' on AArch64.
      
      Use the new notdirty_call_before() and notdirty_call_after()
      functions to correctly handle the update to notdirty memory
      in the atomic codepath.
      
      Cc: qemu-stable@nongnu.org
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 1511201308-23580-3-git-send-email-peter.maydell@linaro.org
      34d49937
    • Peter Maydell's avatar
      exec.c: Factor out before/after actions for notdirty memory writes · 27266271
      Peter Maydell authored
      
      The function notdirty_mem_write() has a sequence of actions
      it has to do before and after the actual business of writing
      data to host RAM to ensure that dirty flags are correctly
      updated and we flush any TCG translations for the region.
      We need to do this also in other places that write directly
      to host RAM, most notably the TCG atomic helper functions.
      Pull out the before and after pieces into their own functions.
      
      We use an API where the prepare function stashes the various
      bits of information about the write into a struct for the
      complete function to use, because in the calls for the atomic
      helpers the place where the complete function will be called
      doesn't have the information to hand.
      
      Cc: qemu-stable@nongnu.org
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Reviewed-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      Message-id: 1511201308-23580-2-git-send-email-peter.maydell@linaro.org
      27266271
    • Peter Maydell's avatar
      Merge remote-tracking branch 'remotes/mdroth/tags/qga-pull-2017-11-20-tag' into staging · a61d3439
      Peter Maydell authored
      
      qemu-ga patch queue for 2.11
      
      * fix potential overflow in network interface stats reporting
      
      # gpg: Signature made Mon 20 Nov 2017 20:56:05 GMT
      # gpg:                using RSA key 0x3353C9CEF108B584
      # gpg: Good signature from "Michael Roth <flukshun@gmail.com>"
      # gpg:                 aka "Michael Roth <mdroth@utexas.edu>"
      # gpg:                 aka "Michael Roth <mdroth@linux.vnet.ibm.com>"
      # Primary key fingerprint: CEAC C9E1 5534 EBAB B82D  3FA0 3353 C9CE F108 B584
      
      * remotes/mdroth/tags/qga-pull-2017-11-20-tag:
        qga: replace GetIfEntry with GetIfEntry2 for interface stats
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      a61d3439
    • Peter Maydell's avatar
      Merge remote-tracking branch 'remotes/riku/tags/pull-linux-user-20171120' into staging · 1b4e6e8c
      Peter Maydell authored
      
      late linux-user fixes for Qemu 2.11
      
      # gpg: Signature made Mon 20 Nov 2017 21:19:00 GMT
      # gpg:                using RSA key 0xB44890DEDE3C9BC0
      # gpg: Good signature from "Riku Voipio <riku.voipio@iki.fi>"
      # gpg:                 aka "Riku Voipio <riku.voipio@linaro.org>"
      # Primary key fingerprint: FF82 03C8 C391 98AE 0581  41EF B448 90DE DE3C 9BC0
      
      * remotes/riku/tags/pull-linux-user-20171120:
        linux-user: Fix calculation of auxv length
        linux-user: Handle rt_sigaction correctly for SPARC
        linux-user/sparc: Put address for data faults where linux-user expects it
        linux-user/ppc: Report correct fault address for data faults
        linux-user/s390x: Mask si_addr for SIGSEGV
        linux-user: return EINVAL from prctl(PR_*_SECCOMP)
        linux-user: fix 'finshed' typo in comment
        linux-user/syscall.c: Handle SH4's exceptional alignment for p{read, write}64
        linux-user: Handle TARGET_MAP_STACK and TARGET_MAP_HUGETLB
        linux-user/hppa: Fix TARGET_F_RDLCK, TARGET_F_WRLCK, TARGET_F_UNLCK
        linux-user/hppa: Fix TARGET_MAP_TYPE
        linux-user/hppa: Fix typo for TARGET_NR_epoll_wait
        linux-user/hppa: Fix cpu_clone_regs
        linux-user/hppa: Fix TARGET_SA_* defines
        linux-user: Restrict usage of sa_restorer
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      1b4e6e8c
    • Peter Maydell's avatar
      Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20171120' into staging · 5f49d73c
      Peter Maydell authored
      
      target-arm queue:
       * hw/arm: Silence xlnx-ep108 deprecation warning during tests
       * hw/arm/aspeed: Unlock SCU when running kernel
       * arm: check regime, not current state, for ATS write PAR format
       * nvic: Fix ARMv7M MPU_RBAR reads
       * target/arm: Report GICv3 sysregs present in ID registers if needed
      
      # gpg: Signature made Mon 20 Nov 2017 17:35:25 GMT
      # gpg:                using RSA key 0x3C2525ED14360CDE
      # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
      # gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
      # gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
      # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE
      
      * remotes/pmaydell/tags/pull-target-arm-20171120:
        hw/arm: Silence xlnx-ep108 deprecation warning during tests
        hw/arm/aspeed: Unlock SCU when running kernel
        arm: check regime, not current state, for ATS write PAR format
        nvic: Fix ARMv7M MPU_RBAR reads
        target/arm: Report GICv3 sysregs present in ID registers if needed
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      5f49d73c
  2. Nov 20, 2017
  3. Nov 19, 2017
    • Greg Kurz's avatar
      spapr: reset DRCs after devices · 82512483
      Greg Kurz authored
      
      A DRC with a pending unplug request releases its associated device at
      machine reset time.
      
      In the case of LMB, when all DRCs for a DIMM device have been reset,
      the DIMM gets unplugged, causing guest memory to disappear. This may
      be very confusing for anything still using this memory.
      
      This is exactly what happens with vhost backends, and QEMU aborts
      with:
      
      qemu-system-ppc64: used ring relocated for ring 2
      qemu-system-ppc64: qemu/hw/virtio/vhost.c:649: vhost_commit: Assertion
       `r >= 0' failed.
      
      The issue is that each DRC registers a QEMU reset handler, and we
      don't control the order in which these handlers are called (ie,
      a LMB DRC will unplug a DIMM before the virtio device using the
      memory on this DIMM could stop its vhost backend).
      
      To avoid such situations, let's reset DRCs after all devices
      have been reset.
      
      Reported-by: default avatarMallesh N. Koti <mallesh@linux.vnet.ibm.com>
      Signed-off-by: default avatarGreg Kurz <groug@kaod.org>
      Reviewed-by: default avatarDaniel Henrique Barboza <danielhb@linux.vnet.ibm.com>
      Reviewed-by: default avatarMichael Roth <mdroth@linux.vnet.ibm.com>
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      82512483
    • Suraj Jitindar Singh's avatar
      target/ppc: Update setting of cpu features to account for compat modes · 7abd43ba
      Suraj Jitindar Singh authored
      
      The device tree nodes ibm,arch-vec-5-platform-support and ibm,pa-features
      are used to communicate features of the cpu to the guest operating
      system. The properties of each of these are determined based on the
      selected cpu model and the availability of hypervisor features.
      Currently the compatibility mode of the cpu is not taken into account.
      
      The ibm,arch-vec-5-platform-support node is used to communicate the
      level of support for various ISAv3 processor features to the guest
      before CAS to inform the guests' request. The available mmu mode should
      only be hash unless the cpu is a POWER9 which is not in a prePOWER9
      compat mode, in which case the available modes depend on the
      accelerator and the hypervisor capabilities.
      
      The ibm,pa-featues node is used to communicate the level of cpu support
      for various features to the guest os. This should only contain features
      relevant to the operating mode of the processor, that is the selected
      cpu model taking into account any compat mode. This means that the
      compat mode should be taken into account when choosing the properties of
      ibm,pa-features and they should match the compat mode selected, or the
      cpu model selected if no compat mode.
      
      Update the setting of these cpu features in the device tree as described
      above to properly take into account any compat mode. We use the
      ppc_check_compat function which takes into account the current processor
      model and the cpu compat mode.
      
      Signed-off-by: default avatarSuraj Jitindar Singh <sjitindarsingh@gmail.com>
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      7abd43ba
  4. Nov 17, 2017
Loading