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  1. Aug 23, 2011
  2. Aug 21, 2011
  3. Aug 07, 2011
  4. Aug 05, 2011
  5. Jul 30, 2011
    • Blue Swirl's avatar
      exec.h cleanup · 3e457172
      Blue Swirl authored
      
      Move softmmu_exec.h include directives from target-*/exec.h to
      target-*/op_helper.c. Move also various other stuff only used in
      op_helper.c there.
      
      Define global env in dyngen-exec.h.
      
      For i386, move wrappers for segment and FPU helpers from user-exec.c
      to op_helper.c. Implement raise_exception_err_env() to handle dynamic
      CPUState. Move the function declarations to cpu.h since they can be
      used outside of op_helper.c context.
      
      LM32, s390x, UniCore32: remove unused cpu_halted(), regs_to_env() and
      env_to_regs().
      
      ARM: make raise_exception() static.
      
      Convert
      #include "exec.h"
      to
      #include "cpu.h"
      #include "dyngen-exec.h"
      and remove now unused target-*/exec.h.
      
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
      3e457172
  6. Jul 12, 2011
  7. Jun 26, 2011
  8. Jun 20, 2011
  9. Jun 17, 2011
    • Alexander Graf's avatar
      PPC: move TLBs to their own arrays · 1c53accc
      Alexander Graf authored
      
      Until now, we've created a union over multiple different TLB types and
      allocated that union. While it's a waste of memory (and cache) to allocate
      TLB information for a TLB type with much information when you only need
      little, it also inflicts another issue.
      
      With the new KVM API, we can now share the TLB between KVM and qemu, but
      for that to work we need to have both be in the same layout. We can't just
      stretch it over to fit some internal different TLB representation.
      
      Hence this patch moves all TLB types to their own array, allowing us to only
      address and allocate exactly the boundaries required for the specific TLB
      type at hand.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      1c53accc
    • Alexander Graf's avatar
      PPC: E500: Use MAS registers instead of internal TLB representation · d1e256fe
      Alexander Graf authored
      
      The natural format for e500 cores to do TLB manipulation with are the MAS
      registers. Instead of converting them into some internal representation
      and back again when the guest reads them, we can just keep the data
      identical to the way the guest passed it to us.
      
      The main advantage of this approach is that we're getting closer to being
      able to share MMU data with KVM using shared memory, so that we don't need
      to copy lots of MMU data back and forth all the time. For this to work
      however, another patch is required that gets rid of the TLB union, as that
      destroys our memory layout that needs to be identical with the kernel one.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      d1e256fe
    • Alexander Graf's avatar
      PPC: Only set lower 32bits with mtmsr · 8018dc63
      Alexander Graf authored
      
      As Nathan pointed out correctly, the mtmsr instruction does not modify
      the high 32 bits of MSR. It also doesn't matter if SF is set or not,
      the instruction always behaves the same.
      
      This patch moves it a bit closer to the spec.
      
      Reported-by: default avatarNathan Whitehorn <nwhitehorn@freebsd.org>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      8018dc63
    • Hervé Poussineau's avatar
      target-ppc: Handle memory-forced I/O controller access · 826e7b82
      Hervé Poussineau authored
      
      On at least the PowerPC 601, a direct-store (T=1) with bus unit ID 0x07F
      is special-cased as memory-forced I/O controller access. It is supposed
      to be checked immediately if T=1, bypassing all protection mechanisms
      and acting cache-inhibited and global.
      
      Signed-off-by: default avatarHervé Poussineau <hpoussin@reactos.org>
      
      Simplified by avoiding reindentation. Added explanatory comments.
      
      Cc: Alexander Graf <agraf@suse.de>
      Signed-off-by: default avatarAndreas Färber <andreas.faerber@web.de>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      826e7b82
  10. Jun 08, 2011
  11. Jun 03, 2011
  12. May 22, 2011
  13. May 20, 2011
    • David Gibson's avatar
      Fix a bug in mtsr/mtsrin emulation on ppc64 · decb4714
      David Gibson authored
      
      Early ppc64 CPUs include a hack to partially simulate the ppc32 segment
      registers, by translating writes to them into writes to the SLB.  This is
      not used by any current Linux kernel, but it is used by the openbios used
      in the qemu mac99 model.
      
      Commit 81762d6d, cleaning up the SLB
      handling introduced a bug in this code, breaking the openbios currently in
      qemu.  Specifically, there was an off by one error bitshuffling the
      register format used by mtsr into the format needed for the SLB load,
      causing the flag bits to end up in the wrong place.  This caused the
      storage keys to be wrong under openbios, meaning that the translation code
      incorrectly thought a legitimate access was a permission violation.
      
      This patch fixes the bug, at the same time it fixes some build bug in the
      MMU debugging code (only exposed when DEBUG_MMU is enabled).
      
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      decb4714
    • Stefan Weil's avatar
      w32: Fix compilation and replace non-portable usage of ulong · 6d42fb31
      Stefan Weil authored
      
      ulong is undefined for w32 (and maybe other) compilations.
      Replace it by uintptr_t (which also fixes compilation for w64
      and is a better choice for pointer to integer conversions).
      
      Cc: Aurelien Jarno <aurelien@aurel32.net>
      Signed-off-by: default avatarStefan Weil <weil@mail.berlios.de>
      Reviewed-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      6d42fb31
  14. May 11, 2011
    • Alexander Graf's avatar
      PPC: Implement e500 (FSL) MMU · 01662f3e
      Alexander Graf authored
      
      Most of the code to support e500 style MMUs is already in place, but
      we're missing on some of the special TLB0-TLB1 handling code and slightly
      different TLB modification.
      
      This patch adds support for the FSL style MMU.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      01662f3e
    • Alexander Graf's avatar
      PPC: Add another 64 bits to instruction feature mask · a5858d7a
      Alexander Graf authored
      
      To enable quick runtime detection of instruction groups to the currently
      selected CPU emulation, we have a feature mask of what exactly the respective
      instruction supports.
      
      This feature mask is 64 bits long and we just successfully exceeded those 64
      bits. To add more features, we need to think of something.
      
      The easiest solution that came to my mind was to simply add another 64 bits
      that we can also match on. Since the comparison is only done on start of the
      qemu process to generate an internal opcode calling table, we should be fine
      on any performance penalties here.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      a5858d7a
    • Alexander Graf's avatar
      PPC: Add GS MSR definition · 71afeb61
      Alexander Graf authored
      
      The BookE specification defines MSR bit 28 as Guest State. Add it
      to the list of MSR macros.
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      71afeb61
  15. May 09, 2011
    • Alexander Graf's avatar
      kvm: ppc: detect old headers · 64e07be5
      Alexander Graf authored
      
      When compiling Qemu with older kernel headers, the PVR setting
      mechanism isn't available yet. Unfortunately, back then I didn't add
      a capability we could check against, so all we can do is add a configure
      test to see if we support PVR setting. For BookE, we don't care yet.
      
      This fixes compilation errors with KVM enabled on older kernel headers
      (like 2.6.32).
      
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      64e07be5
    • Scott Wood's avatar
      monitor: add PPC BookE SPRs · 90dc8812
      Scott Wood authored
      
      Read them via KVM_GET_SREGS in kvm_arch_get_registers(),
      and display them in "info registers".
      
      Also get CR and PID from the existing KVM_GET_REGS.
      
      Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      90dc8812
    • Scott Wood's avatar
      kvm: ppc: fixes for KVM_SET_SREGS on init · 5666ca4a
      Scott Wood authored
      
      Classic/server ppc has had SREGS for a while now (though I think not
      always?), but it's still missing for booke.  Check the capability before
      calling KVM_SET_SREGS.
      
      Without this, booke kvm fails to boot as of commit
      84b4915d (kvm: Handle kvm_init_vcpu
      errors).
      
      Also, don't write random stack state into the non-PVR sregs fields --
      have kvm fill it in first.
      
      Eventually booke will have sregs and it will have its own capability to
      be tested here.  However, we will want a way for platform code to request
      to look like the actual CPU we're running on, especially if SoC devices
      are being directly assigned.
      
      Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      5666ca4a
  16. May 08, 2011
  17. Apr 20, 2011
  18. Apr 17, 2011
    • Aurelien Jarno's avatar
      target-ppc: fix SPE comparison functions · 019702c8
      Aurelien Jarno authored
      
      efstst*() functions are fast SPE funtions which do not take into account
      special values (infinites, NaN, etc.), while efscmp*() functions are
      IEEE754 compliant.
      
      Given that float32_*() functions are IEEE754 compliant, the efscmp*()
      functions are correctly implemented, while efstst*() are not. This
      patch reverse the implementation of this two groups of functions and
      fix the comments. It also use float32_eq() instead of float32_eq_quiet()
      as qNaNs should not be ignored.
      
      Cc: Alexander Graf <agraf@suse.de>
      Cc: Nathan Froyd <froydnj@codesourcery.com>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      019702c8
    • Aurelien Jarno's avatar
      softfloat: rename float*_eq() into float*_eq_quiet() · 211315fb
      Aurelien Jarno authored
      
      float*_eq functions have a different semantics than other comparison
      functions. Fix that by first renaming float*_quiet() into float*_eq_quiet().
      
      Note that it is purely mechanical, and the behaviour should be unchanged.
      That said it clearly highlight problems due to this different semantics,
      they are fixed later in this patch series.
      
      Cc: Alexander Graf <agraf@suse.de>
      Acked-by: default avatarEdgar E. Iglesias <edgar.iglesias@gmail.com>
      Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      211315fb
  19. Apr 12, 2011
  20. Apr 09, 2011
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