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  1. Aug 21, 2020
  2. Aug 19, 2020
    • Peter Maydell's avatar
      Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2020-08-11' into staging · 1d806cef
      Peter Maydell authored
      
      Block patches for 5.1.0-rc4:
      - Fix abort when running a backup job on an image whose size is not
        aligned to the backup job's cluster size
      
      # gpg: Signature made Tue 11 Aug 2020 10:29:27 BST
      # gpg:                using RSA key 91BEB60A30DB3E8857D11829F407DB0061D5CF40
      # gpg:                issuer "mreitz@redhat.com"
      # gpg: Good signature from "Max Reitz <mreitz@redhat.com>" [full]
      # Primary key fingerprint: 91BE B60A 30DB 3E88 57D1  1829 F407 DB00 61D5 CF40
      
      * remotes/maxreitz/tags/pull-block-2020-08-11:
        iotests: add test for unaligned granularity bitmap backup
        block/block-copy: always align copied region to cluster size
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      1d806cef
  3. Aug 18, 2020
  4. Aug 11, 2020
  5. Aug 10, 2020
  6. Aug 05, 2020
  7. Aug 04, 2020
  8. Aug 03, 2020
    • Peter Maydell's avatar
      Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200803' into staging · 5c1c3e4f
      Peter Maydell authored
      
      target-arm queue:
       * hw/timer/imx_epit: Avoid assertion when CR.SWR is written
       * netduino2, netduinoplus2, microbit: set system_clock_scale so that
         SysTick running on the CPU clock works
       * target/arm: Avoid maybe-uninitialized warning with gcc 4.9
       * target/arm: Fix AddPAC error indication
       * Make AIRCR.SYSRESETREQ actually reset the system for the
         microbit, mps2-*, musca-*, netduino* boards
      
      # gpg: Signature made Mon 03 Aug 2020 20:29:17 BST
      # gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
      # gpg:                issuer "peter.maydell@linaro.org"
      # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
      # gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
      # gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
      # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE
      
      * remotes/pmaydell/tags/pull-target-arm-20200803:
        hw/timer/imx_epit: Avoid assertion when CR.SWR is written
        hw/arm/nrf51_soc: Set system_clock_scale
        target/arm: Avoid maybe-uninitialized warning with gcc 4.9
        target/arm: Fix AddPAC error indication
        msf2-soc, stellaris: Don't wire up SYSRESETREQ
        hw/intc/armv7m_nvic: Provide default "reset the system" behaviour for SYSRESETREQ
        include/hw/irq.h: New function qemu_irq_is_connected()
        hw/arm/netduino2, netduinoplus2: Set system_clock_scale
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      5c1c3e4f
    • Peter Maydell's avatar
      hw/timer/imx_epit: Avoid assertion when CR.SWR is written · 13557fd3
      Peter Maydell authored
      The imx_epit device has a software-controllable reset triggered by
      setting the SWR bit in the CR register. An error in commit cc2722ec
      means that we will end up assert()ing if the guest does this, because
      the code in imx_epit_write() starts ptimer transactions, and then
      imx_epit_reset() also starts ptimer transactions, triggering
      "ptimer_transaction_begin: Assertion `!s->in_transaction' failed".
      
      The cleanest way to avoid this double-transaction is to move the
      start-transaction for the CR write handling down below the check of
      the SWR bit.
      
      Fixes: https://bugs.launchpad.net/qemu/+bug/1880424
      
      
      Fixes: cc2722ec
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
      Message-id: 20200727154550.3409-1-peter.maydell@linaro.org
      13557fd3
    • Peter Maydell's avatar
      hw/arm/nrf51_soc: Set system_clock_scale · ce4f70e8
      Peter Maydell authored
      
      The nrf51 SoC model wasn't setting the system_clock_scale
      global.which meant that if guest code used the systick timer in "use
      the processor clock" mode it would hang because time never advances.
      
      Set the global to match the documented CPU clock speed for this SoC.
      
      This SoC in fact doesn't have a SysTick timer (which is the only thing
      currently that cares about the system_clock_scale), because it's
      a configurable option in the Cortex-M0. However our Cortex-M0 and
      thus our nrf51 and our micro:bit board do provide a SysTick, so
      we ought to provide a functional one rather than a broken one.
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
      Message-id: 20200727193458.31250-1-peter.maydell@linaro.org
      ce4f70e8
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