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  1. May 19, 2022
    • Peter Maydell's avatar
      target/arm/helper.c: Delete stray obsolete comment · 1a13efcc
      Peter Maydell authored
      
      In commit 88ce6c6e we switched from directly fishing the number
      of breakpoints and watchpoints out of the ID register fields to
      abstracting out functions to do this job, but we forgot to delete the
      now-obsolete comment in define_debug_regs() about the relation
      between the ID field value and the actual number of breakpoints and
      watchpoints.  Delete the obsolete comment.
      
      Reported-by: default avatarCHRIS HOWARD <cvz185@web.de>
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 20220513131801.4082712-1-peter.maydell@linaro.org
      1a13efcc
    • Philippe Mathieu-Daudé's avatar
      hw/adc/zynq-xadc: Use qemu_irq typedef · 6e76d35f
      Philippe Mathieu-Daudé authored
      
      Except hw/core/irq.c which implements the forward-declared opaque
      qemu_irq structure, hw/adc/zynq-xadc.{c,h} are the only files not
      using the typedef. Fix this single exception.
      
      Signed-off-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
      Reviewed-by: default avatarBernhard Beschow <shentey@gmail.com>
      Message-id: 20220509202035.50335-1-philippe.mathieu.daude@gmail.com
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      6e76d35f
    • Chris Howard's avatar
      Fix aarch64 debug register names. · e1be11a5
      Chris Howard authored
      
      Give all the debug registers their correct names including the
      index, rather than having multiple registers all with the
      same name string, which is confusing when viewed over the
      gdbstub interface.
      
      Signed-off-by: default avatarCHRIS HOWARD <cvz185@web.de>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 4127D8CA-D54A-47C7-A039-0DB7361E30C0@web.de
      [PMM: expanded commit message]
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      e1be11a5
    • Peter Maydell's avatar
      hw/intc/arm_gicv3: Provide ich_num_aprs() · 5d55f827
      Peter Maydell authored
      
      We previously open-coded the expression for the number of virtual APR
      registers and the assertion that it was not going to cause us to
      overflow the cs->ich_apr[] array.  Factor this out into a new
      ich_num_aprs() function, for consistency with the icc_num_aprs()
      function we just added for the physical APR handling.
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 20220512151457.3899052-7-peter.maydell@linaro.org
      Message-id: 20220506162129.2896966-6-peter.maydell@linaro.org
      5d55f827
    • Peter Maydell's avatar
      hw/intc/arm_gicv3: Use correct number of priority bits for the CPU · 39f29e59
      Peter Maydell authored
      
      Make the GICv3 set its number of bits of physical priority from the
      implementation-specific value provided in the CPU state struct, in
      the same way we already do for virtual priority bits.  Because this
      would be a migration compatibility break, we provide a property
      force-8-bit-prio which is enabled for 7.0 and earlier versioned board
      models to retain the legacy "always use 8 bits" behaviour.
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 20220512151457.3899052-6-peter.maydell@linaro.org
      Message-id: 20220506162129.2896966-5-peter.maydell@linaro.org
      39f29e59
    • Peter Maydell's avatar
      hw/intc/arm_gicv3: Support configurable number of physical priority bits · 84597ff3
      Peter Maydell authored
      
      The GICv3 code has always supported a configurable number of virtual
      priority and preemption bits, but our implementation currently
      hardcodes the number of physical priority bits at 8.  This is not
      what most hardware implementations provide; for instance the
      Cortex-A53 provides only 5 bits of physical priority.
      
      Make the number of physical priority/preemption bits driven by fields
      in the GICv3CPUState, the way that we already do for virtual
      priority/preemption bits.  We set cs->pribits to 8, so there is no
      behavioural change in this commit.  A following commit will add the
      machinery for CPUs to set this to the correct value for their
      implementation.
      
      Note that changing the number of priority bits would be a migration
      compatibility break, because the semantics of the icc_apr[][] array
      changes.
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 20220512151457.3899052-5-peter.maydell@linaro.org
      Message-id: 20220506162129.2896966-4-peter.maydell@linaro.org
      84597ff3
    • Peter Maydell's avatar
      hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant · 9774c0f7
      Peter Maydell authored
      
      The GIC_MIN_BPR constant defines the minimum BPR value that the TCG
      emulated GICv3 supports.  We're currently using this also as the
      value we reset the KVM GICv3 ICC_BPR registers to, but this is only
      right by accident.
      
      We want to make the emulated GICv3 use a configurable number of
      priority bits, which means that GIC_MIN_BPR will no longer be a
      constant.  Replace the uses in the KVM reset code with literal 0,
      plus a constant explaining why this is reasonable.
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 20220512151457.3899052-4-peter.maydell@linaro.org
      Message-id: 20220506162129.2896966-3-peter.maydell@linaro.org
      9774c0f7
    • Peter Maydell's avatar
      hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1 · 9c6f933e
      Peter Maydell authored
      
      As noted in the comment, the PRIbits field in ICV_CTLR_EL1 is
      supposed to match the ICH_VTR_EL2 PRIbits setting; that is, it is the
      virtual priority bit setting, not the physical priority bit setting.
      (For QEMU currently we always implement 8 bits of physical priority,
      so the PRIbits field was previously 7, since it is defined to be
      "priority bits - 1".)
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 20220512151457.3899052-3-peter.maydell@linaro.org
      Message-id: 20220506162129.2896966-2-peter.maydell@linaro.org
      9c6f933e
    • Peter Maydell's avatar
      hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parameters · 272f75e8
      Peter Maydell authored
      
      We allow a GICv3 to be connected to any CPU, but we don't do anything
      to handle the case where the CPU type doesn't in hardware have a
      GICv3 CPU interface and so the various GIC configuration fields
      (gic_num_lrs, vprebits, vpribits) are not specified.
      
      The current behaviour is that we will add the EL1 CPU interface
      registers, but will not put in the EL2 CPU interface registers, even
      if the CPU has EL2, which will leave the GIC in a broken state and
      probably result in the guest crashing as it tries to set it up.  This
      only affects the virt board when using the cortex-a15 or cortex-a7
      CPU types (both 32-bit) with -machine gic-version=3 (or 'max')
      and -machine virtualization=on.
      
      Instead of failing to set up the EL2 registers, if the CPU doesn't
      define the GIC configuration set it to a reasonable default, matching
      the standard configuration for most Arm CPUs.
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 20220512151457.3899052-2-peter.maydell@linaro.org
      272f75e8
    • Peter Maydell's avatar
      target/arm: Drop unsupported_encoding() macro · 3d52472f
      Peter Maydell authored
      
      The unsupported_encoding() macro logs a LOG_UNIMP message and then
      generates code to raise the usual exception for an unallocated
      encoding.  Back when we were still implementing the A64 decoder this
      was helpful for flagging up when guest code was using something we
      hadn't yet implemented.  Now we completely cover the A64 instruction
      set it is barely used.  The only remaining uses are for five
      instructions whose semantics are "UNDEF, unless being run under
      external halting debug":
       * HLT (when not being used for semihosting)
       * DCPSR1, DCPS2, DCPS3
       * DRPS
      
      QEMU doesn't implement external halting debug, so for us the UNDEF is
      the architecturally correct behaviour (because it's not possible to
      execute these instructions with halting debug enabled).  The
      LOG_UNIMP doesn't serve a useful purpose; replace these uses of
      unsupported_encoding() with unallocated_encoding(), and delete the
      macro.
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 20220509160443.3561604-1-peter.maydell@linaro.org
      3d52472f
    • Peter Maydell's avatar
      target/arm: Implement FEAT_IDST · 75662f36
      Peter Maydell authored
      
      The Armv8.4 feature FEAT_IDST specifies that exceptions generated by
      read accesses to the feature ID space should report a syndrome code
      of 0x18 (EC_SYSTEMREGISTERTRAP) rather than 0x00 (EC_UNCATEGORIZED).
      The feature ID space is defined to be:
       op0 == 3, op1 == {0,1,3}, CRn == 0, CRm == {0-7}, op2 == {0-7}
      
      In our implementation we might return the EC_UNCATEGORIZED syndrome
      value for a system register access in four cases:
       * no reginfo struct in the hashtable
       * cp_access_ok() fails (ie ri->access doesn't permit the access)
       * ri->accessfn returns CP_ACCESS_TRAP_UNCATEGORIZED at runtime
       * ri->type includes ARM_CP_RAISES_EXC, and the readfn raises
         an UNDEF exception at runtime
      
      We have very few regdefs that set ARM_CP_RAISES_EXC, and none of
      them are in the feature ID space. (In the unlikely event that any
      are added in future they would need to take care of setting the
      correct syndrome themselves.) This patch deals with the other
      three cases, and enables FEAT_IDST for AArch64 -cpu max.
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 20220509155457.3560724-1-peter.maydell@linaro.org
      75662f36
    • Peter Maydell's avatar
      target/arm: Enable FEAT_S2FWB for -cpu max · e04bf5a7
      Peter Maydell authored
      
      Enable the FEAT_S2FWB for -cpu max. Since FEAT_S2FWB requires that
      CLIDR_EL1.{LoUU,LoUIS} are zero, we explicitly squash these (the
      inherited CLIDR_EL1 value from the Cortex-A57 has them as 1).
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 20220505183950.2781801-5-peter.maydell@linaro.org
      e04bf5a7
    • Peter Maydell's avatar
      target/arm: Implement FEAT_S2FWB · 8c7e17ef
      Peter Maydell authored
      
      Implement the handling of FEAT_S2FWB; the meat of this is in the new
      combined_attrs_fwb() function which combines S1 and S2 attributes
      when HCR_EL2.FWB is set.
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 20220505183950.2781801-4-peter.maydell@linaro.org
      8c7e17ef
    • Peter Maydell's avatar
      target/arm: Factor out FWB=0 specific part of combine_cacheattrs() · 4a0b47c8
      Peter Maydell authored
      
      Factor out the part of combine_cacheattrs() that is specific to
      handling HCR_EL2.FWB == 0.  This is the part where we combine the
      memory type and cacheability attributes.
      
      The "force Outer Shareable for Device or Normal Inner-NC Outer-NC"
      logic remains in combine_cacheattrs() because it holds regardless
      (this is the equivalent of the pseudocode EffectiveShareability()
      function).
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 20220505183950.2781801-3-peter.maydell@linaro.org
      4a0b47c8
    • Peter Maydell's avatar
      target/arm: Postpone interpretation of stage 2 descriptor attribute bits · 9f225e60
      Peter Maydell authored
      
      In the original Arm v8 two-stage translation, both stage 1 and stage
      2 specify memory attributes (memory type, cacheability,
      shareability); these are then combined to produce the overall memory
      attributes for the whole stage 1+2 access.  In QEMU we implement this
      by having get_phys_addr() fill in an ARMCacheAttrs struct, and we
      convert both the stage 1 and stage 2 attribute bit formats to the
      same encoding (an 8-bit attribute value matching the MAIR_EL1 fields,
      plus a 2-bit shareability value).
      
      The new FEAT_S2FWB feature allows the guest to enable a different
      interpretation of the attribute bits in the stage 2 descriptors.
      These bits can now be used to control details of how the stage 1 and
      2 attributes should be combined (for instance they can say "always
      use the stage 1 attributes" or "ignore the stage 1 attributes and
      always be Device memory").  This means we need to pass the raw bit
      information for stage 2 down to the function which combines the stage
      1 and stage 2 information.
      
      Add a field to ARMCacheAttrs that indicates whether the attrs field
      should be interpreted as MAIR format, or as the raw stage 2 attribute
      bits from the descriptor, and store the appropriate values when
      filling in cacheattrs.
      
      We only need to interpret the attrs field in a few places:
       * in do_ats_write(), where we know to expect a MAIR value
         (there is no ATS instruction to do a stage-2-only walk)
       * in S1_ptw_translate(), where we want to know whether the
         combined S1 + S2 attributes indicate Device memory that
         should provoke a fault
       * in combine_cacheattrs(), which does the S1 + S2 combining
      Update those places accordingly.
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 20220505183950.2781801-2-peter.maydell@linaro.org
      9f225e60
  2. May 18, 2022
    • Richard Henderson's avatar
      Merge tag 'artist-cursor-fix-final-pull-request' of... · 78ac2eeb
      Richard Henderson authored
      Merge tag 'artist-cursor-fix-final-pull-request' of https://github.com/hdeller/qemu-hppa
      
       into staging
      
      hppa: Artist graphics driver fixes for HP-UX and keyboard fix in firmware boot console
      
      This series updates the SeaBIOS-hppa firmware to version 5, in which additional
      HP fonts were added to the firmware and the firmware boot console was fixed to
      accept input from the emulated PS/2 keyboard when running in graphical mode
      (serial console was working before already). To test use the "-boot menu=on"
      qemu option.
      
      The artist graphics card driver got various fixes when running the X11-Windows
      on HP-UX:
      - fixes the horizontal and vertical postioning of the X11 cursor with HP-UX
      - allows X11 to blank the screen (e.g. screensaver)
      - allows the X11 driver to turn the X11 cursor on/off
      
      Signed-off-by: default avatarHelge Deller <deller@gmx.de>
      
      --
      Changes compared to version 2 of this series:
      - Fixed style issues in the X-cursor positioning patch (noticed by Mark Cave-Ayland)
      
      Changes compared to version 1 of this series:
      - Added some Acked-by's from Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
      - SeaBIOS-hppa v5 instead of v4 (PS/2 keyboard now works in boot console)
      - integrated artist X11 X-cusor positioning fix (which was sent serperately before)
      
      --
      This series should apply cleanly on git head and can be pulled for testing
      from: https://github.com/hdeller/qemu-hppa.git   artist-cursor-fix-final
      
      # -----BEGIN PGP SIGNATURE-----
      #
      # iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCYoUcLwAKCRD3ErUQojoP
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      # =ZrTm
      # -----END PGP SIGNATURE-----
      # gpg: Signature made Wed 18 May 2022 09:17:51 AM PDT
      # gpg:                using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F
      # gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown]
      # gpg:                 aka "Helge Deller <deller@kernel.org>" [unknown]
      # gpg: WARNING: This key is not certified with a trusted signature!
      # gpg:          There is no indication that the signature belongs to the owner.
      # Primary key fingerprint: 4544 8228 2CD9 10DB EF3D  25F8 3E5F 3D04 A7A2 4603
      #      Subkey fingerprint: BCE9 123E 1AD2 9F07 C049  BBDE F712 B510 A23A 0F5F
      
      * tag 'artist-cursor-fix-final-pull-request' of https://github.com/hdeller/qemu-hppa
      
      :
        artist: Fix X cursor position calculation in X11
        artist: Emulate screen blanking
        artist: Allow to turn cursor on or off
        artist: Fix vertical X11 cursor position in HP-UX
        artist: Use human-readable variable names instead of reg_xxx
        artist: Introduce constant for max cursor size
        seabios-hppa: Update SeaBIOS-hppa to VERSION 5
      
      Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      78ac2eeb
    • Richard Henderson's avatar
      Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging · bcf0a3a4
      Richard Henderson authored
      # -----BEGIN PGP SIGNATURE-----
      # Version: GnuPG v1
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      # =5fRf
      # -----END PGP SIGNATURE-----
      # gpg: Signature made Tue 17 May 2022 01:50:04 AM PDT
      # gpg:                using RSA key EF04965B398D6211
      # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [undefined]
      # gpg: WARNING: This key is not certified with a trusted signature!
      # gpg:          There is no indication that the signature belongs to the owner.
      # Primary key fingerprint: 215D 46F4 8246 689E C77F  3562 EF04 965B 398D 6211
      
      * tag 'net-pull-request' of https://github.com/jasowang/qemu
      
      :
        tulip: Assign default MAC address if not specified
        net/vmnet: update hmp-commands.hx
        net/vmnet: update qemu-options.hx
        net/vmnet: implement bridged mode (vmnet-bridged)
        net/vmnet: implement host mode (vmnet-host)
        net/vmnet: implement shared mode (vmnet-shared)
        net/vmnet: add vmnet backends to qapi/net
        net/vmnet: add vmnet dependency and customizable option
      
      Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      bcf0a3a4
  3. May 17, 2022
  4. May 16, 2022
    • Richard Henderson's avatar
      Merge tag 'for_upstream' of git://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging · eec39811
      Richard Henderson authored
      
      virtio,pc,pci: fixes,cleanups,features
      
      most of CXL support
      fixes, cleanups all over the place
      
      Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      
      # -----BEGIN PGP SIGNATURE-----
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      # =xdSk
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      # gpg: Signature made Mon 16 May 2022 01:48:50 PM PDT
      # gpg:                using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
      # gpg:                issuer "mst@redhat.com"
      # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [undefined]
      # gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>" [undefined]
      # gpg: WARNING: This key is not certified with a trusted signature!
      # gpg:          There is no indication that the signature belongs to the owner.
      # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
      #      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469
      
      * tag 'for_upstream' of git://git.kernel.org/pub/scm/virt/kvm/mst/qemu
      
      : (86 commits)
        vhost-user-scsi: avoid unlink(NULL) with fd passing
        virtio-net: don't handle mq request in userspace handler for vhost-vdpa
        vhost-vdpa: change name and polarity for vhost_vdpa_one_time_request()
        vhost-vdpa: backend feature should set only once
        vhost-net: fix improper cleanup in vhost_net_start
        vhost-vdpa: fix improper cleanup in net_init_vhost_vdpa
        virtio-net: align ctrl_vq index for non-mq guest for vhost_vdpa
        virtio-net: setup vhost_dev and notifiers for cvq only when feature is negotiated
        hw/i386/amd_iommu: Fix IOMMU event log encoding errors
        hw/i386: Make pic a property of common x86 base machine type
        hw/i386: Make pit a property of common x86 base machine type
        include/hw/pci/pcie_host: Correct PCIE_MMCFG_SIZE_MAX
        include/hw/pci/pcie_host: Correct PCIE_MMCFG_BUS_MASK
        docs/vhost-user: Clarifications for VHOST_USER_ADD/REM_MEM_REG
        vhost-user: more master/slave things
        virtio: add vhost support for virtio devices
        virtio: drop name parameter for virtio_init()
        virtio/vhost-user: dynamically assign VhostUserHostNotifiers
        hw/virtio/vhost-user: don't suppress F_CONFIG when supported
        include/hw: start documenting the vhost API
        ...
      
      Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      eec39811
    • Richard Henderson's avatar
      Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging · afdb415e
      Richard Henderson authored
      * fix WHPX debugging
      * misc qga-vss fixes
      * remove the deprecated CPU model 'Icelake-Client'
      * support for x86 architectural LBR
      * remove deprecated properties
      * replace deprecated -soundhw with -audio
      
      # -----BEGIN PGP SIGNATURE-----
      #
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      # QHJlZGhhdC5jb20ACgkQv/vSX3jHroN2Igf/bFs+yluOikt0eFNmXYnshrGBWPXr
      # oam0iumPox34vTzZnjpSjF6tJGxHWOgi+wbgIvbwOYHA/ONxx8akW580j+1VhEWa
      # X29VyUzjZBffgFtmlF4fM74/ELYm7s4c1a1/D9TpVP6Dr0fSWbMujbx4dfeVstvf
      # sONN+A8sVxaNdV9QKPE6BvqfMlPLoCiigrOetf6iY1KuUtkQDF8xDB0MdzdutqAQ
      # szAtQ0rrzjxDx9EuGN1SECFM1/riDUbtOOoA9g2C7gGKrx3/iUc6pzrkIcAfWLFK
      # xXbH7+6Wynia0cbUxnrvRdY4daMIxm4N3wUvN7szXgF9kxYxeQcsdgGsNA==
      # =n4lu
      # -----END PGP SIGNATURE-----
      # gpg: Signature made Sat 14 May 2022 03:34:06 AM PDT
      # gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
      # gpg:                issuer "pbonzini@redhat.com"
      # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [undefined]
      # gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [undefined]
      # gpg: WARNING: This key is not certified with a trusted signature!
      # gpg:          There is no indication that the signature belongs to the owner.
      # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
      #      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83
      
      * tag 'for-upstream' of https://gitlab.com/bonzini/qemu
      
      : (23 commits)
        configure: remove duplicate help messages
        configure: remove another dead variable
        build: remove useless dependency
        introduce -audio as a replacement for -soundhw
        soundhw: move help handling to vl.c
        soundhw: unify initialization for ISA and PCI soundhw
        soundhw: extract soundhw help to a separate function
        soundhw: remove ability to create multiple soundcards
        rng: make opened property read-only
        crypto: make loaded property read-only
        target/i386: Support Arch LBR in CPUID enumeration
        target/i386: introduce helper to access supported CPUID
        target/i386: Enable Arch LBR migration states in vmstate
        target/i386: Add MSR access interface for Arch LBR
        target/i386: Add XSAVES support for Arch LBR
        target/i386: Enable support for XSAVES based features
        target/i386: Add kvm_get_one_msr helper
        target/i386: Add lbr-fmt vPMU option to support guest LBR
        qdev-properties: Add a new macro with bitmask check for uint64_t property
        i386/cpu: Remove the deprecated cpu model 'Icelake-Client'
        ...
      
      Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      afdb415e
    • Stefan Hajnoczi's avatar
      vhost-user-scsi: avoid unlink(NULL) with fd passing · 6852c21d
      Stefan Hajnoczi authored
      
      Commit 747421e9 ("Implements Backend
      Program conventions for vhost-user-scsi") introduced fd-passing support
      as part of implementing the vhost-user backend program conventions.
      
      When fd passing is used the UNIX domain socket path is NULL and we must
      not call unlink(2).
      
      The unlink(2) call is necessary when the listen socket, lsock, was
      created successfully since that means the UNIX domain socket is visible
      in the file system.
      
      Fixes: Coverity CID 1488353
      Fixes: 747421e9 ("Implements Backend Program conventions for vhost-user-scsi")
      Signed-off-by: default avatarStefan Hajnoczi <stefanha@redhat.com>
      Message-Id: <20220516155701.1789638-1-stefanha@redhat.com>
      Reviewed-by: default avatarRaphael Norwitz <raphael.norwitz@nutanix.com>
      Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      6852c21d
    • Si-Wei Liu's avatar
      virtio-net: don't handle mq request in userspace handler for vhost-vdpa · 2a7888cc
      Si-Wei Liu authored
      
      virtio_queue_host_notifier_read() tends to read pending event
      left behind on ioeventfd in the vhost_net_stop() path, and
      attempts to handle outstanding kicks from userspace vq handler.
      However, in the ctrl_vq handler, virtio_net_handle_mq() has a
      recursive call into virtio_net_set_status(), which may lead to
      segmentation fault as shown in below stack trace:
      
      0  0x000055f800df1780 in qdev_get_parent_bus (dev=0x0) at ../hw/core/qdev.c:376
      1  0x000055f800c68ad8 in virtio_bus_device_iommu_enabled (vdev=vdev@entry=0x0) at ../hw/virtio/virtio-bus.c:331
      2  0x000055f800d70d7f in vhost_memory_unmap (dev=<optimized out>) at ../hw/virtio/vhost.c:318
      3  0x000055f800d70d7f in vhost_memory_unmap (dev=<optimized out>, buffer=0x7fc19bec5240, len=2052, is_write=1, access_len=2052) at ../hw/virtio/vhost.c:336
      4  0x000055f800d71867 in vhost_virtqueue_stop (dev=dev@entry=0x55f8037ccc30, vdev=vdev@entry=0x55f8044ec590, vq=0x55f8037cceb0, idx=0) at ../hw/virtio/vhost.c:1241
      5  0x000055f800d7406c in vhost_dev_stop (hdev=hdev@entry=0x55f8037ccc30, vdev=vdev@entry=0x55f8044ec590) at ../hw/virtio/vhost.c:1839
      6  0x000055f800bf00a7 in vhost_net_stop_one (net=0x55f8037ccc30, dev=0x55f8044ec590) at ../hw/net/vhost_net.c:315
      7  0x000055f800bf0678 in vhost_net_stop (dev=dev@entry=0x55f8044ec590, ncs=0x55f80452bae0, data_queue_pairs=data_queue_pairs@entry=7, cvq=cvq@entry=1)
         at ../hw/net/vhost_net.c:423
      8  0x000055f800d4e628 in virtio_net_set_status (status=<optimized out>, n=0x55f8044ec590) at ../hw/net/virtio-net.c:296
      9  0x000055f800d4e628 in virtio_net_set_status (vdev=vdev@entry=0x55f8044ec590, status=15 '\017') at ../hw/net/virtio-net.c:370
      10 0x000055f800d534d8 in virtio_net_handle_ctrl (iov_cnt=<optimized out>, iov=<optimized out>, cmd=0 '\000', n=0x55f8044ec590) at ../hw/net/virtio-net.c:1408
      11 0x000055f800d534d8 in virtio_net_handle_ctrl (vdev=0x55f8044ec590, vq=0x7fc1a7e888d0) at ../hw/net/virtio-net.c:1452
      12 0x000055f800d69f37 in virtio_queue_host_notifier_read (vq=0x7fc1a7e888d0) at ../hw/virtio/virtio.c:2331
      13 0x000055f800d69f37 in virtio_queue_host_notifier_read (n=n@entry=0x7fc1a7e8894c) at ../hw/virtio/virtio.c:3575
      14 0x000055f800c688e6 in virtio_bus_cleanup_host_notifier (bus=<optimized out>, n=n@entry=14) at ../hw/virtio/virtio-bus.c:312
      15 0x000055f800d73106 in vhost_dev_disable_notifiers (hdev=hdev@entry=0x55f8035b51b0, vdev=vdev@entry=0x55f8044ec590)
         at ../../../include/hw/virtio/virtio-bus.h:35
      16 0x000055f800bf00b2 in vhost_net_stop_one (net=0x55f8035b51b0, dev=0x55f8044ec590) at ../hw/net/vhost_net.c:316
      17 0x000055f800bf0678 in vhost_net_stop (dev=dev@entry=0x55f8044ec590, ncs=0x55f80452bae0, data_queue_pairs=data_queue_pairs@entry=7, cvq=cvq@entry=1)
         at ../hw/net/vhost_net.c:423
      18 0x000055f800d4e628 in virtio_net_set_status (status=<optimized out>, n=0x55f8044ec590) at ../hw/net/virtio-net.c:296
      19 0x000055f800d4e628 in virtio_net_set_status (vdev=0x55f8044ec590, status=15 '\017') at ../hw/net/virtio-net.c:370
      20 0x000055f800d6c4b2 in virtio_set_status (vdev=0x55f8044ec590, val=<optimized out>) at ../hw/virtio/virtio.c:1945
      21 0x000055f800d11d9d in vm_state_notify (running=running@entry=false, state=state@entry=RUN_STATE_SHUTDOWN) at ../softmmu/runstate.c:333
      22 0x000055f800d04e7a in do_vm_stop (state=state@entry=RUN_STATE_SHUTDOWN, send_stop=send_stop@entry=false) at ../softmmu/cpus.c:262
      23 0x000055f800d04e99 in vm_shutdown () at ../softmmu/cpus.c:280
      24 0x000055f800d126af in qemu_cleanup () at ../softmmu/runstate.c:812
      25 0x000055f800ad5b13 in main (argc=<optimized out>, argv=<optimized out>, envp=<optimized out>) at ../softmmu/main.c:51
      
      For now, temporarily disable handling MQ request from the ctrl_vq
      userspace hanlder to avoid the recursive virtio_net_set_status()
      call. Some rework is needed to allow changing the number of
      queues without going through a full virtio_net_set_status cycle,
      particularly for vhost-vdpa backend.
      
      This patch will need to be reverted as soon as future patches of
      having the change of #queues handled in userspace is merged.
      
      Fixes: 40237840 ("vhost-vdpa: multiqueue support")
      Signed-off-by: default avatarSi-Wei Liu <si-wei.liu@oracle.com>
      Acked-by: default avatarJason Wang <jasowang@redhat.com>
      Message-Id: <1651890498-24478-8-git-send-email-si-wei.liu@oracle.com>
      Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      2a7888cc
    • Si-Wei Liu's avatar
      vhost-vdpa: change name and polarity for vhost_vdpa_one_time_request() · d71b0609
      Si-Wei Liu authored
      
      The name vhost_vdpa_one_time_request() was confusing. No
      matter whatever it returns, its typical occurrence had
      always been at requests that only need to be applied once.
      And the name didn't suggest what it actually checks for.
      Change it to vhost_vdpa_first_dev() with polarity flipped
      for better readibility of code. That way it is able to
      reflect what the check is really about.
      
      This call is applicable to request which performs operation
      only once, before queues are set up, and usually at the beginning
      of the caller function. Document the requirement for it in place.
      
      Signed-off-by: default avatarSi-Wei Liu <si-wei.liu@oracle.com>
      Message-Id: <1651890498-24478-7-git-send-email-si-wei.liu@oracle.com>
      Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      Reviewed-by: default avatarStefano Garzarella <sgarzare@redhat.com>
      Acked-by: default avatarJason Wang <jasowang@redhat.com>
      d71b0609
    • Si-Wei Liu's avatar
      vhost-vdpa: backend feature should set only once · 6aee7e42
      Si-Wei Liu authored
      
      The vhost_vdpa_one_time_request() branch in
      vhost_vdpa_set_backend_cap() incorrectly sends down
      ioctls on vhost_dev with non-zero index. This may
      end up with multiple VHOST_SET_BACKEND_FEATURES
      ioctl calls sent down on the vhost-vdpa fd that is
      shared between all these vhost_dev's.
      
      To fix it, send down ioctl only once via the first
      vhost_dev with index 0. Toggle the polarity of the
      vhost_vdpa_one_time_request() test should do the
      trick.
      
      Fixes: 4d191cfd ("vhost-vdpa: classify one time request")
      Signed-off-by: default avatarSi-Wei Liu <si-wei.liu@oracle.com>
      Reviewed-by: default avatarStefano Garzarella <sgarzare@redhat.com>
      Acked-by: default avatarJason Wang <jasowang@redhat.com>
      Acked-by: default avatarEugenio Pérez <eperezma@redhat.com>
      Message-Id: <1651890498-24478-6-git-send-email-si-wei.liu@oracle.com>
      Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      6aee7e42
    • Si-Wei Liu's avatar
      vhost-net: fix improper cleanup in vhost_net_start · 6f3910b5
      Si-Wei Liu authored
      
      vhost_net_start() missed a corresponding stop_one() upon error from
      vhost_set_vring_enable(). While at it, make the error handling for
      err_start more robust. No real issue was found due to this though.
      
      Signed-off-by: default avatarSi-Wei Liu <si-wei.liu@oracle.com>
      Acked-by: default avatarJason Wang <jasowang@redhat.com>
      Message-Id: <1651890498-24478-5-git-send-email-si-wei.liu@oracle.com>
      Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      6f3910b5
    • Si-Wei Liu's avatar
      vhost-vdpa: fix improper cleanup in net_init_vhost_vdpa · 9bd05507
      Si-Wei Liu authored
      
      ... such that no memory leaks on dangling net clients in case of
      error.
      
      Signed-off-by: default avatarSi-Wei Liu <si-wei.liu@oracle.com>
      Acked-by: default avatarJason Wang <jasowang@redhat.com>
      Message-Id: <1651890498-24478-4-git-send-email-si-wei.liu@oracle.com>
      Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      9bd05507
    • Si-Wei Liu's avatar
      virtio-net: align ctrl_vq index for non-mq guest for vhost_vdpa · 68b0a639
      Si-Wei Liu authored
      
      With MQ enabled vdpa device and non-MQ supporting guest e.g.
      booting vdpa with mq=on over OVMF of single vqp, below assert
      failure is seen:
      
      ../hw/virtio/vhost-vdpa.c:560: vhost_vdpa_get_vq_index: Assertion `idx >= dev->vq_index && idx < dev->vq_index + dev->nvqs' failed.
      
      0  0x00007f8ce3ff3387 in raise () at /lib64/libc.so.6
      1  0x00007f8ce3ff4a78 in abort () at /lib64/libc.so.6
      2  0x00007f8ce3fec1a6 in __assert_fail_base () at /lib64/libc.so.6
      3  0x00007f8ce3fec252 in  () at /lib64/libc.so.6
      4  0x0000558f52d79421 in vhost_vdpa_get_vq_index (dev=<optimized out>, idx=<optimized out>) at ../hw/virtio/vhost-vdpa.c:563
      5  0x0000558f52d79421 in vhost_vdpa_get_vq_index (dev=<optimized out>, idx=<optimized out>) at ../hw/virtio/vhost-vdpa.c:558
      6  0x0000558f52d7329a in vhost_virtqueue_mask (hdev=0x558f55c01800, vdev=0x558f568f91f0, n=2, mask=<optimized out>) at ../hw/virtio/vhost.c:1557
      7  0x0000558f52c6b89a in virtio_pci_set_guest_notifier (d=d@entry=0x558f568f0f60, n=n@entry=2, assign=assign@entry=true, with_irqfd=with_irqfd@entry=false)
         at ../hw/virtio/virtio-pci.c:974
      8  0x0000558f52c6c0d8 in virtio_pci_set_guest_notifiers (d=0x558f568f0f60, nvqs=3, assign=true) at ../hw/virtio/virtio-pci.c:1019
      9  0x0000558f52bf091d in vhost_net_start (dev=dev@entry=0x558f568f91f0, ncs=0x558f56937cd0, data_queue_pairs=data_queue_pairs@entry=1, cvq=cvq@entry=1)
         at ../hw/net/vhost_net.c:361
      10 0x0000558f52d4e5e7 in virtio_net_set_status (status=<optimized out>, n=0x558f568f91f0) at ../hw/net/virtio-net.c:289
      11 0x0000558f52d4e5e7 in virtio_net_set_status (vdev=0x558f568f91f0, status=15 '\017') at ../hw/net/virtio-net.c:370
      12 0x0000558f52d6c4b2 in virtio_set_status (vdev=vdev@entry=0x558f568f91f0, val=val@entry=15 '\017') at ../hw/virtio/virtio.c:1945
      13 0x0000558f52c69eff in virtio_pci_common_write (opaque=0x558f568f0f60, addr=<optimized out>, val=<optimized out>, size=<optimized out>) at ../hw/virtio/virtio-pci.c:1292
      14 0x0000558f52d15d6e in memory_region_write_accessor (mr=0x558f568f19d0, addr=20, value=<optimized out>, size=1, shift=<optimized out>, mask=<optimized out>, attrs=...)
         at ../softmmu/memory.c:492
      15 0x0000558f52d127de in access_with_adjusted_size (addr=addr@entry=20, value=value@entry=0x7f8cdbffe748, size=size@entry=1, access_size_min=<optimized out>, access_size_max=<optimized out>, access_fn=0x558f52d15cf0 <memory_region_write_accessor>, mr=0x558f568f19d0, attrs=...) at ../softmmu/memory.c:554
      16 0x0000558f52d157ef in memory_region_dispatch_write (mr=mr@entry=0x558f568f19d0, addr=20, data=<optimized out>, op=<optimized out>, attrs=attrs@entry=...)
         at ../softmmu/memory.c:1504
      17 0x0000558f52d078e7 in flatview_write_continue (fv=fv@entry=0x7f8accbc3b90, addr=addr@entry=103079215124, attrs=..., ptr=ptr@entry=0x7f8ce6300028, len=len@entry=1, addr1=<optimized out>, l=<optimized out>, mr=0x558f568f19d0) at /home/opc/qemu-upstream/include/qemu/host-utils.h:165
      18 0x0000558f52d07b06 in flatview_write (fv=0x7f8accbc3b90, addr=103079215124, attrs=..., buf=0x7f8ce6300028, len=1) at ../softmmu/physmem.c:2822
      19 0x0000558f52d0b36b in address_space_write (as=<optimized out>, addr=<optimized out>, attrs=..., buf=buf@entry=0x7f8ce6300028, len=<optimized out>)
         at ../softmmu/physmem.c:2914
      20 0x0000558f52d0b3da in address_space_rw (as=<optimized out>, addr=<optimized out>, attrs=...,
         attrs@entry=..., buf=buf@entry=0x7f8ce6300028, len=<optimized out>, is_write=<optimized out>) at ../softmmu/physmem.c:2924
      21 0x0000558f52dced09 in kvm_cpu_exec (cpu=cpu@entry=0x558f55c2da60) at ../accel/kvm/kvm-all.c:2903
      22 0x0000558f52dcfabd in kvm_vcpu_thread_fn (arg=arg@entry=0x558f55c2da60) at ../accel/kvm/kvm-accel-ops.c:49
      23 0x0000558f52f9f04a in qemu_thread_start (args=<optimized out>) at ../util/qemu-thread-posix.c:556
      24 0x00007f8ce4392ea5 in start_thread () at /lib64/libpthread.so.0
      25 0x00007f8ce40bb9fd in clone () at /lib64/libc.so.6
      
      The cause for the assert failure is due to that the vhost_dev index
      for the ctrl vq was not aligned with actual one in use by the guest.
      Upon multiqueue feature negotiation in virtio_net_set_multiqueue(),
      if guest doesn't support multiqueue, the guest vq layout would shrink
      to a single queue pair, consisting of 3 vqs in total (rx, tx and ctrl).
      This results in ctrl_vq taking a different vhost_dev group index than
      the default. We can map vq to the correct vhost_dev group by checking
      if MQ is supported by guest and successfully negotiated. Since the
      MQ feature is only present along with CTRL_VQ, we ensure the index
      2 is only meant for the control vq while MQ is not supported by guest.
      
      Fixes: 22288fe5 ("virtio-net: vhost control virtqueue support")
      Suggested-by: default avatarJason Wang <jasowang@redhat.com>
      Signed-off-by: default avatarSi-Wei Liu <si-wei.liu@oracle.com>
      Acked-by: default avatarJason Wang <jasowang@redhat.com>
      Message-Id: <1651890498-24478-3-git-send-email-si-wei.liu@oracle.com>
      Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      68b0a639
    • Si-Wei Liu's avatar
      virtio-net: setup vhost_dev and notifiers for cvq only when feature is negotiated · aa858194
      Si-Wei Liu authored
      
      When the control virtqueue feature is absent or not negotiated,
      vhost_net_start() still tries to set up vhost_dev and install
      vhost notifiers for the control virtqueue, which results in
      erroneous ioctl calls with incorrect queue index sending down
      to driver. Do that only when needed.
      
      Fixes: 22288fe5 ("virtio-net: vhost control virtqueue support")
      Signed-off-by: default avatarSi-Wei Liu <si-wei.liu@oracle.com>
      Acked-by: default avatarJason Wang <jasowang@redhat.com>
      Message-Id: <1651890498-24478-2-git-send-email-si-wei.liu@oracle.com>
      Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      aa858194
    • Wei Huang's avatar
      hw/i386/amd_iommu: Fix IOMMU event log encoding errors · 18aa91cd
      Wei Huang authored
      
      Coverity issues several UNINIT warnings against amd_iommu.c [1]. This
      patch fixes them by clearing evt before encoding. On top of it, this
      patch changes the event log size to 16 bytes per IOMMU specification,
      and fixes the event log entry format in amdvi_encode_event().
      
      [1] CID 1487116/1487200/1487190/1487232/1487115/1487258
      
      Reported-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Signed-off-by: default avatarWei Huang <wei.huang2@amd.com>
      Message-Id: <20220422055146.3312226-1-wei.huang2@amd.com>
      Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Acked-by: default avatarJason Wang <jasowang@redhat.com>
      Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      18aa91cd
    • Xiaoyao Li's avatar
      hw/i386: Make pic a property of common x86 base machine type · c300bbe8
      Xiaoyao Li authored
      
      Legacy PIC (8259) cannot be supported for TDX guests since TDX module
      doesn't allow directly interrupt injection.  Using posted interrupts
      for the PIC is not a viable option as the guest BIOS/kernel will not
      do EOI for PIC IRQs, i.e. will leave the vIRR bit set.
      
      Make PIC the property of common x86 machine type. Hence all x86
      machines, including microvm, can disable it.
      
      Signed-off-by: default avatarXiaoyao Li <xiaoyao.li@intel.com>
      Reviewed-by: default avatarSergio Lopez <slp@redhat.com>
      Message-Id: <20220310122811.807794-3-xiaoyao.li@intel.com>
      Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      c300bbe8
    • Xiaoyao Li's avatar
      hw/i386: Make pit a property of common x86 base machine type · 9dee7e51
      Xiaoyao Li authored
      
      Both pc and microvm have pit property individually. Let's just make it
      the property of common x86 base machine type.
      
      Signed-off-by: default avatarXiaoyao Li <xiaoyao.li@intel.com>
      Reviewed-by: default avatarSergio Lopez <slp@redhat.com>
      Message-Id: <20220310122811.807794-2-xiaoyao.li@intel.com>
      Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      9dee7e51
    • Francisco Iglesias's avatar
      include/hw/pci/pcie_host: Correct PCIE_MMCFG_SIZE_MAX · 1f1a7b22
      Francisco Iglesias authored
      
      According to 7.2.2 in [1] bit 27 is the last bit that can be part of the
      bus number, this makes the ECAM max size equal to '1 << 28'. This patch
      restores back this value into the PCIE_MMCFG_SIZE_MAX define (which was
      changed in commit 58d5b22b ("ppc4xx: Add device models found in PPC440
      core SoCs")).
      
      [1] PCI Express® Base Specification Revision 5.0 Version 1.0
      
      Signed-off-by: default avatarFrancisco Iglesias <frasse.iglesias@gmail.com>
      Message-Id: <20220411221836.17699-3-frasse.iglesias@gmail.com>
      Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      1f1a7b22
    • Francisco Iglesias's avatar
      include/hw/pci/pcie_host: Correct PCIE_MMCFG_BUS_MASK · 8e58f6ec
      Francisco Iglesias authored
      
      According to [1] address bits 27 - 20 are mapped to the bus number (the
      TLPs bus number field is 8 bits). Below is the formula taken from Table
      7-1 in [1].
      
      "
      Memory Address | PCI Express Configuration Space
      A[(20+n-1):20] | Bus Number, 1 ≤ n ≤ 8
      "
      
      [1] PCI Express® Base Specification Revision 5.0 Version 1.0
      
      Signed-off-by: default avatarFrancisco Iglesias <frasse.iglesias@gmail.com>
      Message-Id: <20220411221836.17699-2-frasse.iglesias@gmail.com>
      Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      8e58f6ec
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