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  1. Mar 04, 2022
  2. Mar 03, 2022
    • Peter Maydell's avatar
      Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20220303' into staging · 5959ef7d
      Peter Maydell authored
      
      Fifth RISC-V PR for QEMU 7.0
      
       * Fixup checks for ext_zb[abcs]
       * Add AIA support for virt machine
       * Increase maximum number of CPUs in virt machine
       * Fixup OpenTitan SPI address
       * Add support for zfinx, zdinx and zhinx{min} extensions
      
      # gpg: Signature made Thu 03 Mar 2022 05:26:55 GMT
      # gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
      # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
      # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054
      
      * remotes/alistair/tags/pull-riscv-to-apply-20220303:
        target/riscv: expose zfinx, zdinx, zhinx{min} properties
        target/riscv: add support for zhinx/zhinxmin
        target/riscv: add support for zdinx
        target/riscv: add support for zfinx
        target/riscv: hardwire mstatus.FS to zero when enable zfinx
        target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
        hw: riscv: opentitan: fixup SPI addresses
        hw/riscv: virt: Increase maximum number of allowed CPUs
        docs/system: riscv: Document AIA options for virt machine
        hw/riscv: virt: Add optional AIA IMSIC support to virt machine
        hw/intc: Add RISC-V AIA IMSIC device emulation
        hw/riscv: virt: Add optional AIA APLIC support to virt machine
        target/riscv: fix inverted checks for ext_zb[abcs]
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      5959ef7d
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