target/riscv: Split misa.mxl and misa.ext
The hw representation of misa.mxl is at the high bits of the misa csr. Representing this in the same way inside QEMU results in overly complex code trying to check that field. Reviewed-by:LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by:
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- linux-user/elfload.c 1 addition, 1 deletionlinux-user/elfload.c
- linux-user/riscv/cpu_loop.c 1 addition, 1 deletionlinux-user/riscv/cpu_loop.c
- target/riscv/cpu.c 45 additions, 33 deletionstarget/riscv/cpu.c
- target/riscv/cpu.h 8 additions, 7 deletionstarget/riscv/cpu.h
- target/riscv/csr.c 29 additions, 15 deletionstarget/riscv/csr.c
- target/riscv/gdbstub.c 4 additions, 4 deletionstarget/riscv/gdbstub.c
- target/riscv/machine.c 6 additions, 4 deletionstarget/riscv/machine.c
- target/riscv/translate.c 6 additions, 4 deletionstarget/riscv/translate.c
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