Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210624-2' into staging
Third RISC-V PR for 6.1 release
- Fix MISA in the DisasContext
- Fix GDB CSR XML generation
- QOMify the SiFive UART
- Add support for the OpenTitan timer
# gpg: Signature made Thu 24 Jun 2021 13:00:26 BST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20210624-2:
hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
hw/timer: Initial commit of Ibex Timer
hw/char/ibex_uart: Make the register layout private
hw/char: QOMify sifive_uart
hw/char: Consistent function names for sifive_uart
target/riscv: gdbstub: Fix dynamic CSR XML generation
target/riscv: Use target_ulong for the DisasContext misa
Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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- MAINTAINERS 2 additions, 4 deletionsMAINTAINERS
- hw/char/ibex_uart.c 37 additions, 0 deletionshw/char/ibex_uart.c
- hw/char/sifive_uart.c 124 additions, 28 deletionshw/char/sifive_uart.c
- hw/riscv/opentitan.c 11 additions, 3 deletionshw/riscv/opentitan.c
- hw/timer/ibex_timer.c 305 additions, 0 deletionshw/timer/ibex_timer.c
- hw/timer/meson.build 1 addition, 0 deletionshw/timer/meson.build
- include/hw/char/ibex_uart.h 0 additions, 37 deletionsinclude/hw/char/ibex_uart.h
- include/hw/char/sifive_uart.h 5 additions, 6 deletionsinclude/hw/char/sifive_uart.h
- include/hw/riscv/opentitan.h 4 additions, 1 deletioninclude/hw/riscv/opentitan.h
- include/hw/timer/ibex_timer.h 52 additions, 0 deletionsinclude/hw/timer/ibex_timer.h
- target/riscv/gdbstub.c 1 addition, 1 deletiontarget/riscv/gdbstub.c
- target/riscv/translate.c 1 addition, 1 deletiontarget/riscv/translate.c
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