target/riscv: Consolidate RV32/64 32-bit instructions
This patch removes the insn32-64.decode decode file and consolidates the instructions into the general RISC-V insn32.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit softmmu before we execute the 64-bit only instructions. This allows us to include the 32-bit instructions in the 64-bit build, while also ensuring that 32-bit only software can not execute the instructions. Signed-off-by:Alistair Francis <alistair.francis@wdc.com> Reviewed-by:
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- target/riscv/fpu_helper.c 8 additions, 8 deletionstarget/riscv/fpu_helper.c
- target/riscv/helper.h 8 additions, 10 deletionstarget/riscv/helper.h
- target/riscv/insn32-64.decode 0 additions, 88 deletionstarget/riscv/insn32-64.decode
- target/riscv/insn32.decode 66 additions, 1 deletiontarget/riscv/insn32.decode
- target/riscv/insn_trans/trans_rva.c.inc 11 additions, 3 deletionstarget/riscv/insn_trans/trans_rva.c.inc
- target/riscv/insn_trans/trans_rvd.c.inc 14 additions, 3 deletionstarget/riscv/insn_trans/trans_rvd.c.inc
- target/riscv/insn_trans/trans_rvf.c.inc 4 additions, 2 deletionstarget/riscv/insn_trans/trans_rvf.c.inc
- target/riscv/insn_trans/trans_rvh.c.inc 6 additions, 2 deletionstarget/riscv/insn_trans/trans_rvh.c.inc
- target/riscv/insn_trans/trans_rvi.c.inc 12 additions, 4 deletionstarget/riscv/insn_trans/trans_rvi.c.inc
- target/riscv/insn_trans/trans_rvm.c.inc 10 additions, 2 deletionstarget/riscv/insn_trans/trans_rvm.c.inc
- target/riscv/insn_trans/trans_rvv.c.inc 20 additions, 19 deletionstarget/riscv/insn_trans/trans_rvv.c.inc
- target/riscv/meson.build 1 addition, 1 deletiontarget/riscv/meson.build
- target/riscv/translate.c 6 additions, 3 deletionstarget/riscv/translate.c
- target/riscv/vector_helper.c 0 additions, 4 deletionstarget/riscv/vector_helper.c
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