target/riscv: Implement hgeie and hgeip CSRs
The hgeie and hgeip CSRs are required for emulating an external interrupt controller capable of injecting virtual external interrupt to Guest/VM running at VS-level. Signed-off-by:Anup Patel <anup.patel@wdc.com> Signed-off-by:
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- target/riscv/cpu.c 47 additions, 20 deletionstarget/riscv/cpu.c
- target/riscv/cpu.h 5 additions, 0 deletionstarget/riscv/cpu.h
- target/riscv/cpu_bits.h 1 addition, 0 deletionstarget/riscv/cpu_bits.h
- target/riscv/cpu_helper.c 34 additions, 3 deletionstarget/riscv/cpu_helper.c
- target/riscv/csr.c 30 additions, 13 deletionstarget/riscv/csr.c
- target/riscv/machine.c 4 additions, 2 deletionstarget/riscv/machine.c
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