target-arm: A64: Create Instruction Syndromes for Data Aborts
Add support for generating the ISS (Instruction Specific Syndrome) for Data Abort exceptions taken from AArch64. These syndromes are used by hypervisors for example to trap and emulate memory accesses. We save the decoded data out-of-band with the TBs at translation time. When exceptions hit, the extra data attached to the TB is used to recreate the state needed to encode instruction syndromes. This avoids the need to emit moves with every load/store. Based on a suggestion from Peter Maydell. Suggested-by:Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1462464601-10888-2-git-send-email-edgar.iglesias@gmail.com Reviewed-by:
Peter Maydell <peter.maydell@linaro.org> Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
Showing
- target-arm/cpu.h 13 additions, 1 deletiontarget-arm/cpu.h
- target-arm/op_helper.c 43 additions, 6 deletionstarget-arm/op_helper.c
- target-arm/translate-a64.c 118 additions, 22 deletionstarget-arm/translate-a64.c
- target-arm/translate.c 4 additions, 1 deletiontarget-arm/translate.c
- target-arm/translate.h 2 additions, 0 deletionstarget-arm/translate.h
Loading
Please register or sign in to comment