target/riscv: debug: Determine the trigger type from tdata1.type
Current RISC-V debug assumes that only type 2 trigger is supported. To allow more types of triggers to be supported in the future (e.g. type 6 trigger, which is similar to type 2 trigger with additional functionality), we should determine the trigger type from tdata1.type. RV_MAX_TRIGGERS is also introduced in replacement of TRIGGER_TYPE2_NUM. Signed-off-by:Frank Chang <frank.chang@sifive.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
LIU Zhiwei <zhiwei_liu@linux.alibaba.com> [bmeng: fixed MXL_RV128 case, and moved macros to the following patch] Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220909134215.1843865-2-bmeng.cn@gmail.com> Signed-off-by:
Alistair Francis <alistair.francis@wdc.com>
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- target/riscv/cpu.h 1 addition, 1 deletiontarget/riscv/cpu.h
- target/riscv/csr.c 1 addition, 1 deletiontarget/riscv/csr.c
- target/riscv/debug.c 133 additions, 55 deletionstarget/riscv/debug.c
- target/riscv/debug.h 4 additions, 9 deletionstarget/riscv/debug.h
- target/riscv/machine.c 1 addition, 1 deletiontarget/riscv/machine.c
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