Merge tag 'pull-riscv-to-apply-20230306' of https://gitlab.com/palmer-dabbelt/qemu into staging
Sixth RISC-V PR for 8.0 * Support for the Zicbiom, ZCicboz, and Zicbop extensions. * OpenSBI has been updated to version 1.2, see <https://github.com/riscv-software-src/opensbi/releases/tag/v1.2> for the release notes. * Support for setting the virtual address width (ie, sv39/sv48/sv57) on the command line. * Support for ACPI on RISC-V. # -----BEGIN PGP SIGNATURE----- # # iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmQGYGgTHHBhbG1lckBk # YWJiZWx0LmNvbQAKCRAuExnzX7sYidmyEAC6FEMbbFM5D++qR6w6xM6hXgzcrev6 # s1kyRRNVa45uSA78ti/Zi0hsDLNf7ZsNPndF0OIkkO5iAE0OVm3LU7tV1TqKcT82 # Dd9VXxe93zEmfnuJazHrMa54SXPhhnNdWHtKlZ6vBfZpbxgx0FFs50xkCsrM5LQZ # hYHxQUqPWQTvF2MdDHrxCuLcdKl+Wg3ysCcgRh2d049KUBrIu6vNaHC2+AGRjCbj # BkrGCkB82fTmVJjzAcVWQxLoAV12pCbJS4og1GtP8hA7WevtB39tbPin9siBKRZp # QBeiIsg0nebkpmZGrb+xWVwlIBNe9yYwJa0KmveQk8v7L5RIzjM1mtDL91VrVljC # KC2tfT570m0Iq2NoFMb3wd/kESHFzVDM/g+XYqRd4KSoiCNP/RbqYNQBwbMc31Tr # E27xfA1D8w2vem0Rk20x3KgPf1Z5OmGXjq6YObTpnAzG8cZlA37qKBP+ortt5aHX # GZSg3CAwknHHVajd4aaegkPsHxm1tRvoTfh38MwkPSNxaA9GD0nz0k9xaYDmeZ2L # olfanNsaQEwcVUId31+7sAENg1TZU0fnj879/nxkMUCazVTdL8/mz+IoTTx0QCST # 3+9ATWcyJUlmjbDKIs7kr1L+wJdvvHEJggPAbbPI8ekpXaLZvUYOT6ObzYKNAmwY # wELQBn8QKXcLVA== # =5gAt # -----END PGP SIGNATURE----- # gpg: Signature made Mon 06 Mar 2023 21:51:36 GMT # gpg: using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmerdabbelt@google.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 # Subkey fingerprint: 2B3C 3747 4468 43B2 4A94 3A7A 2E13 19F3 5FBB 1889 * tag 'pull-riscv-to-apply-20230306' of https://gitlab.com/palmer-dabbelt/qemu : (22 commits) MAINTAINERS: Add entry for RISC-V ACPI hw/riscv/virt.c: Initialize the ACPI tables hw/riscv/virt: virt-acpi-build.c: Add RHCT Table hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT hw/riscv/virt: Enable basic ACPI infrastructure hw/riscv/virt: Add memmap pointer to RiscVVirtState hw/riscv/virt: Add a switch to disable ACPI hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fields riscv: Correctly set the device-tree entry 'mmu-type' riscv: Introduce satp mode hw capabilities riscv: Allow user to set the satp mode riscv: Change type of valid_vm_1_10_[32|64] to bool riscv: Pass Object to register_cpu_props instead of DeviceState roms/opensbi: Upgrade from v1.1 to v1.2 gitlab/opensbi: Move to docker:stable hw: intc: Use cpu_by_arch_id to fetch CPU state target/riscv: cpu: Implement get_arch_id callback disas/riscv Fix ctzw disassemble hw/riscv/virt.c: add cbo[mz]-block-size fdt properties target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder ... Signed-off-by:Peter Maydell <peter.maydell@linaro.org>
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- .gitlab-ci.d/opensbi.yml 2 additions, 2 deletions.gitlab-ci.d/opensbi.yml
- .gitlab-ci.d/opensbi/Dockerfile 1 addition, 0 deletions.gitlab-ci.d/opensbi/Dockerfile
- MAINTAINERS 12 additions, 6 deletionsMAINTAINERS
- disas/riscv.c 1 addition, 1 deletiondisas/riscv.c
- hw/intc/riscv_aclint.c 8 additions, 8 deletionshw/intc/riscv_aclint.c
- hw/intc/riscv_aplic.c 2 additions, 2 deletionshw/intc/riscv_aplic.c
- hw/intc/riscv_imsic.c 3 additions, 3 deletionshw/intc/riscv_imsic.c
- hw/riscv/Kconfig 1 addition, 0 deletionshw/riscv/Kconfig
- hw/riscv/meson.build 1 addition, 0 deletionshw/riscv/meson.build
- hw/riscv/virt-acpi-build.c 416 additions, 0 deletionshw/riscv/virt-acpi-build.c
- hw/riscv/virt.c 62 additions, 8 deletionshw/riscv/virt.c
- include/hw/riscv/virt.h 6 additions, 0 deletionsinclude/hw/riscv/virt.h
- pc-bios/opensbi-riscv32-generic-fw_dynamic.bin 0 additions, 0 deletionspc-bios/opensbi-riscv32-generic-fw_dynamic.bin
- pc-bios/opensbi-riscv64-generic-fw_dynamic.bin 0 additions, 0 deletionspc-bios/opensbi-riscv64-generic-fw_dynamic.bin
- roms/opensbi 1 addition, 1 deletionroms/opensbi
- target/riscv/cpu.c 289 additions, 14 deletionstarget/riscv/cpu.c
- target/riscv/cpu.h 29 additions, 0 deletionstarget/riscv/cpu.h
- target/riscv/csr.c 14 additions, 15 deletionstarget/riscv/csr.c
- target/riscv/helper.h 5 additions, 0 deletionstarget/riscv/helper.h
- target/riscv/insn32.decode 15 additions, 1 deletiontarget/riscv/insn32.decode
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