target/riscv: Allow generating hlv/hlvx/hsv instructions
Signed-off-by:
Alistair Francis <alistair.francis@wdc.com>
Message-id: 477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com
Message-Id: <477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com>
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- target/riscv/cpu_bits.h 1 addition, 0 deletionstarget/riscv/cpu_bits.h
- target/riscv/helper.h 3 additions, 0 deletionstarget/riscv/helper.h
- target/riscv/insn32-64.decode 5 additions, 0 deletionstarget/riscv/insn32-64.decode
- target/riscv/insn32.decode 11 additions, 0 deletionstarget/riscv/insn32.decode
- target/riscv/insn_trans/trans_rvh.c.inc 340 additions, 0 deletionstarget/riscv/insn_trans/trans_rvh.c.inc
- target/riscv/op_helper.c 114 additions, 0 deletionstarget/riscv/op_helper.c
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