Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-3.2-part2' into staging
RISC-V Updates for 3.2, Part 2
This patch set contains a handful of Michael's CSR-related cleanups,
which should allow us to proceed with more outstanding bug fixes that
depend on them.
Additionally, there is a patch that turns on USB. This works for me
when the kernel has the appropriate drivers (which will soon be in
defconfig) and I pass
-device usb-ehci
-drive id=my_usb_disk,file=usbdisk.img,if=none,format=raw
-device usb-storage,drive=my_usb_disk
to QEMU.
# gpg: Signature made Fri 11 Jan 2019 18:05:02 GMT
# gpg: using RSA key EF4CA1502CCBAB41
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>"
# gpg: aka "Palmer Dabbelt <palmer@sifive.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41
* remotes/palmer/tags/riscv-for-master-3.2-part2:
default-configs: Enable USB support for RISC-V machines
RISC-V: Implement existential predicates for CSRs
RISC-V: Implement atomic mip/sip CSR updates
RISC-V: Implement modular CSR helper interface
Signed-off-by:
Peter Maydell <peter.maydell@linaro.org>
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- default-configs/riscv32-softmmu.mak 1 addition, 0 deletionsdefault-configs/riscv32-softmmu.mak
- default-configs/riscv64-softmmu.mak 1 addition, 0 deletionsdefault-configs/riscv64-softmmu.mak
- target/riscv/Makefile.objs 1 addition, 1 deletiontarget/riscv/Makefile.objs
- target/riscv/cpu.c 6 additions, 0 deletionstarget/riscv/cpu.c
- target/riscv/cpu.h 36 additions, 5 deletionstarget/riscv/cpu.h
- target/riscv/cpu_helper.c 4 additions, 3 deletionstarget/riscv/cpu_helper.c
- target/riscv/csr.c 863 additions, 0 deletionstarget/riscv/csr.c
- target/riscv/gdbstub.c 8 additions, 2 deletionstarget/riscv/gdbstub.c
- target/riscv/op_helper.c 15 additions, 598 deletionstarget/riscv/op_helper.c
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