target/riscv: support for 128-bit shift instructions (6bf4bbed) · Commits · Anton / libtcg · GitLab

Skip to content

GitLab

Explore

Sign in

Primary navigation

Project

L

libtcg
- Activity
- Members
- Labels
- Issues
- Issue boards
- Milestones
- Wiki
- Environments
- Terraform modules
- Incidents

Snippets Groups Projects

6bf4bbed

Commit 6bf4bbed authored 3 years ago by Frédéric Pétrot Committed by Alistair Francis 3 years ago

Downloads
- Patches
- Plain Diff

target/riscv: support for 128-bit shift instructions

Handling shifts for 32, 64 and 128 operation length for RV128, following the
general framework for handling various olens proposed by Richard.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-13-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

parent 57c108b8

No related branches found

No related tags found

No related merge requests found

Changes 4

Hide whitespace changes

Inline Side-by-side

Showing

target/riscv/insn32.decode 10 additions, 0 deletions

target/riscv/insn32.decode
target/riscv/insn_trans/trans_rvb.c.inc 11 additions, 11 deletions

target/riscv/insn_trans/trans_rvb.c.inc
target/riscv/insn_trans/trans_rvi.c.inc 206 additions, 18 deletions

target/riscv/insn_trans/trans_rvi.c.inc
target/riscv/translate.c 43 additions, 15 deletions

target/riscv/translate.c

with 270 additions and 44 deletions

Loading

0% Loading or .

You are about to add 0 people to the discussion. Proceed with caution.

Finish editing this message first!

Please register or sign in to comment