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Commit 5de5b99b authored by Richard Henderson's avatar Richard Henderson Committed by Eduardo Habkost
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target/riscv: Set instance_align on RISCVCPU TypeInfo


Fix alignment of CPURISCVState.vreg.

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Message-Id: <20200916004638.2444147-6-richard.henderson@linaro.org>
Signed-off-by: default avatarEduardo Habkost <ehabkost@redhat.com>
parent 1b49d144
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......@@ -628,6 +628,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.name = TYPE_RISCV_CPU,
.parent = TYPE_CPU,
.instance_size = sizeof(RISCVCPU),
.instance_align = __alignof__(RISCVCPU),
.instance_init = riscv_cpu_init,
.abstract = true,
.class_size = sizeof(RISCVCPUClass),
......
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