Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-20211007' into staging

Third RISC-V PR for QEMU 6.2

 - Add Zb[abcs] instruction support
 - Remove RVB support
 - Bug fix of setting mstatus_hs.[SD|FS] bits
 - Mark some UART devices as 'input'
 - QOMify PolarFire MMUART
 - Fixes for sifive PDMA
 - Mark shakti_c as not user creatable

# gpg: Signature made Wed 06 Oct 2021 11:42:53 PM PDT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]

* remotes/alistair23/tags/pull-riscv-to-apply-20211007: (26 commits)
  hw/riscv: shakti_c: Mark as not user creatable
  hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed
  hw/dma: sifive_pdma: Fix Control.claim bit detection
  hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART
  hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container
  hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition
  hw/char: sifive_uart: Register device in 'input' category
  hw/char: shakti_uart: Register device in 'input' category
  hw/char: ibex_uart: Register device in 'input' category
  target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()
  disas/riscv: Add Zb[abcs] instructions
  target/riscv: Remove RVB (replaced by Zb[abcs])
  target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh
  target/riscv: Add rev8 instruction, removing grev/grevi
  target/riscv: Add a REQUIRE_32BIT macro
  target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
  target/riscv: Reassign instructions to the Zbb-extension
  target/riscv: Add instructions of the Zbc-extension
  target/riscv: Reassign instructions to the Zbs-extension
  target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>