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Commit 33a9a57d authored by Yifei Jiang's avatar Yifei Jiang Committed by Alistair Francis
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target/riscv: raise exception to HS-mode at get_physical_address


VS-stage translation at get_physical_address needs to translate pte
address by G-stage translation. But the G-stage translation error
can not be distinguished from VS-stage translation error in
riscv_cpu_tlb_fill. On migration, destination needs to rebuild pte,
and this G-stage translation error must be handled by HS-mode. So
introduce TRANSLATE_STAGE2_FAIL so that riscv_cpu_tlb_fill could
distinguish and raise it to HS-mode.

Signed-off-by: default avatarYifei Jiang <jiangyifei@huawei.com>
Signed-off-by: default avatarYipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Message-id: 20201014101728.848-1-jiangyifei@huawei.com
[ Change by AF:
 - Clarify the fault_pte_addr shift
]
Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
parent 38bc4e34
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