hw/misc: Add a basic Aspeed LPC controller model
This is a very minimal framework to access registers which are used to configure the AHB memory mapping of the flash chips on the LPC HC Firmware address space. Signed-off-by:Cédric Le Goater <clg@kaod.org> Signed-off-by:
Andrew Jeffery <andrew@aj.id.au> Message-Id: <20210302014317.915120-5-andrew@aj.id.au> Signed-off-by:
Cédric Le Goater <clg@kaod.org>
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- docs/system/arm/aspeed.rst 1 addition, 1 deletiondocs/system/arm/aspeed.rst
- hw/arm/aspeed_ast2600.c 10 additions, 0 deletionshw/arm/aspeed_ast2600.c
- hw/arm/aspeed_soc.c 10 additions, 0 deletionshw/arm/aspeed_soc.c
- hw/misc/aspeed_lpc.c 131 additions, 0 deletionshw/misc/aspeed_lpc.c
- hw/misc/meson.build 6 additions, 1 deletionhw/misc/meson.build
- include/hw/arm/aspeed_soc.h 2 additions, 0 deletionsinclude/hw/arm/aspeed_soc.h
- include/hw/misc/aspeed_lpc.h 32 additions, 0 deletionsinclude/hw/misc/aspeed_lpc.h
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