target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
Signed-off-by:Frank Chang <frank.chang@sifive.com> Acked-by:
Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-75-frank.chang@sifive.com> Signed-off-by:
Alistair Francis <alistair.francis@wdc.com>
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- target/riscv/helper.h 2 additions, 0 deletionstarget/riscv/helper.h
- target/riscv/insn32.decode 4 additions, 0 deletionstarget/riscv/insn32.decode
- target/riscv/insn_trans/trans_rvv.c.inc 40 additions, 0 deletionstarget/riscv/insn_trans/trans_rvv.c.inc
- target/riscv/vector_helper.c 21 additions, 0 deletionstarget/riscv/vector_helper.c
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