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  • Stefan Hajnoczi's avatar
    a7e8e30e
    Merge tag 'pull-target-arm-20230908' of... · a7e8e30e
    Stefan Hajnoczi authored
    Merge tag 'pull-target-arm-20230908' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
    
    target-arm queue:
     * New CPU type: cortex-a710
     * Implement new architectural features:
        - FEAT_PACQARMA3
        - FEAT_EPAC
        - FEAT_Pauth2
        - FEAT_FPAC
        - FEAT_FPACCOMBINE
        - FEAT_TIDCP1
     * Xilinx Versal: Model the CFU/CFI
     * Implement RMR_ELx registers
     * Implement handling of HCR_EL2.TIDCP trap bit
     * arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
     * hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()
     * target/arm: Do not use gen_mte_checkN in trans_STGP
     * arm64: Restore trapless ptimer access
    
    # -----BEGIN PGP SIGNATURE-----
    #
    # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmT7VEkZHHBldGVyLm1h
    # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3v7BEACENUKCxsFHRQSLmQkoBCT9
    # Lc4SJrGCbVUC6b+4s5ligZSWIoFzp/kY6NPpeRYqFa0DCxozd2T5D81/j7TpSo0C
    # wUFkZfUq1nGFJ4K5arYcDwhdTtJvvc07YrSbUqufBp6uNGqhR4YmDWPECqBfOlaj
    # 7bgJM6axsg7FkJJh5zp4cQ4WEfp14MHWRPQWpVTI+9cxNmNymokSVRBhVFkM0Wen
    # WD4C/nYud8bOxpDfR8GkIqJ+UnUMhUNEhp28QmHdwywgg0zLWOE4ysIxo55cM0+0
    # FL3q45PL2e4S24UUx9dkxDBWnKEZ5qpQpPn9F6EhWzfm3n2dqr4uUnfWAEOg6NAi
    # vnGS9MlL7nZo69OM3h8g7yKDfTKYm2vl9HVZ0ytFA6PLoSnaQyQwli58qnLtiid3
    # 17MWPoNQlq6G8tHUTPkrJjdA8XLz0iNPXe5G2kwhuM/S0Lv7ORzDc2pq4qBYLvIw
    # 9nV0oUWqzyE7zH6bRKxbbPw2sMI7c8qQr9QRyZeLHL7HdcY5ExvX9FH+qii5JDR/
    # fZohi1pBoNNwYYTeSRnxgHiQ7OizYq0xQJhrdqcFF9voytZj1yZEZ0mp6Tq0/CIj
    # YkC/vEyLYBqgrJ2JeUjbV3h1RIzQcVaXxnxwGsyMyceACd6MNMmdbjR7bZk0lNIu
    # kh+aFEdKajPp56UseJiKBQ==
    # =5Shq
    # -----END PGP SIGNATURE-----
    # gpg: Signature made Fri 08 Sep 2023 13:05:13 EDT
    # gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
    # gpg:                issuer "peter.maydell@linaro.org"
    # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
    # gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
    # gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
    # gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
    # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE
    
    * tag 'pull-target-arm-20230908' of https://git.linaro.org/people/pmaydell/qemu-arm
    
    : (26 commits)
      arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
      target/arm: Enable SCTLR_EL1.TIDCP for user-only
      target/arm: Implement FEAT_TIDCP1
      target/arm: Implement HCR_EL2.TIDCP
      target/arm: Implement cortex-a710
      target/arm: Implement RMR_ELx
      arm64: Restore trapless ptimer access
      target/arm: Do not use gen_mte_checkN in trans_STGP
      hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG
      hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR
      hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG
      hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG
      hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR
      hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO
      hw/misc: Introduce a model of Xilinx Versal's CFU_APB
      hw/misc: Introduce the Xilinx CFI interface
      hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()
      target/arm: Implement FEAT_FPAC and FEAT_FPACCOMBINE
      target/arm: Inform helpers whether a PAC instruction is 'combined'
      target/arm: Implement FEAT_Pauth2
      ...
    
    Signed-off-by: default avatarStefan Hajnoczi <stefanha@redhat.com>
    a7e8e30e
    History
    Merge tag 'pull-target-arm-20230908' of...
    Stefan Hajnoczi authored
    Merge tag 'pull-target-arm-20230908' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
    
    target-arm queue:
     * New CPU type: cortex-a710
     * Implement new architectural features:
        - FEAT_PACQARMA3
        - FEAT_EPAC
        - FEAT_Pauth2
        - FEAT_FPAC
        - FEAT_FPACCOMBINE
        - FEAT_TIDCP1
     * Xilinx Versal: Model the CFU/CFI
     * Implement RMR_ELx registers
     * Implement handling of HCR_EL2.TIDCP trap bit
     * arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
     * hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()
     * target/arm: Do not use gen_mte_checkN in trans_STGP
     * arm64: Restore trapless ptimer access
    
    # -----BEGIN PGP SIGNATURE-----
    #
    # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmT7VEkZHHBldGVyLm1h
    # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3v7BEACENUKCxsFHRQSLmQkoBCT9
    # Lc4SJrGCbVUC6b+4s5ligZSWIoFzp/kY6NPpeRYqFa0DCxozd2T5D81/j7TpSo0C
    # wUFkZfUq1nGFJ4K5arYcDwhdTtJvvc07YrSbUqufBp6uNGqhR4YmDWPECqBfOlaj
    # 7bgJM6axsg7FkJJh5zp4cQ4WEfp14MHWRPQWpVTI+9cxNmNymokSVRBhVFkM0Wen
    # WD4C/nYud8bOxpDfR8GkIqJ+UnUMhUNEhp28QmHdwywgg0zLWOE4ysIxo55cM0+0
    # FL3q45PL2e4S24UUx9dkxDBWnKEZ5qpQpPn9F6EhWzfm3n2dqr4uUnfWAEOg6NAi
    # vnGS9MlL7nZo69OM3h8g7yKDfTKYm2vl9HVZ0ytFA6PLoSnaQyQwli58qnLtiid3
    # 17MWPoNQlq6G8tHUTPkrJjdA8XLz0iNPXe5G2kwhuM/S0Lv7ORzDc2pq4qBYLvIw
    # 9nV0oUWqzyE7zH6bRKxbbPw2sMI7c8qQr9QRyZeLHL7HdcY5ExvX9FH+qii5JDR/
    # fZohi1pBoNNwYYTeSRnxgHiQ7OizYq0xQJhrdqcFF9voytZj1yZEZ0mp6Tq0/CIj
    # YkC/vEyLYBqgrJ2JeUjbV3h1RIzQcVaXxnxwGsyMyceACd6MNMmdbjR7bZk0lNIu
    # kh+aFEdKajPp56UseJiKBQ==
    # =5Shq
    # -----END PGP SIGNATURE-----
    # gpg: Signature made Fri 08 Sep 2023 13:05:13 EDT
    # gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
    # gpg:                issuer "peter.maydell@linaro.org"
    # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
    # gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
    # gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
    # gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
    # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE
    
    * tag 'pull-target-arm-20230908' of https://git.linaro.org/people/pmaydell/qemu-arm
    
    : (26 commits)
      arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
      target/arm: Enable SCTLR_EL1.TIDCP for user-only
      target/arm: Implement FEAT_TIDCP1
      target/arm: Implement HCR_EL2.TIDCP
      target/arm: Implement cortex-a710
      target/arm: Implement RMR_ELx
      arm64: Restore trapless ptimer access
      target/arm: Do not use gen_mte_checkN in trans_STGP
      hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG
      hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR
      hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG
      hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG
      hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR
      hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO
      hw/misc: Introduce a model of Xilinx Versal's CFU_APB
      hw/misc: Introduce the Xilinx CFI interface
      hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()
      target/arm: Implement FEAT_FPAC and FEAT_FPACCOMBINE
      target/arm: Inform helpers whether a PAC instruction is 'combined'
      target/arm: Implement FEAT_Pauth2
      ...
    
    Signed-off-by: default avatarStefan Hajnoczi <stefanha@redhat.com>