- Replace all ranged case statements with explicit enumerations
- Add alternate forms for lots of builtins we expect from gcc
- Generally, lay on the floor and weep

mips_toIR: fail attempt to decode a branch or jump without its delay …

This (at least partially) fixes angr/angr#71.

Note that there is already code in place
(https://github.com/angr/vex/blob/acccba9/priv/guest_mips_toIR.c#L17239) to
check if the last instruction in the to-be-decoded block is a branch or jump,
in which case the code simply stops decoding *before* that last instruction, so
as not to separate it from the delay slot. However, this check is only applied
to the "next" instruction, but not to the first instruction in the block. So if
only a single instruction is to be decoded, and it happens to be a branch or
jump, the existing code doesn't catch it.

It might be possible to modify the existing code to also catch the single-
instruction case, however that would be a more invasive change (and would
probably also require moving the whole check from the end of the function to
its beginning), so I preferred special-casing the single-instruction case.

these offsets have been sitting on my working branch for a very long time and I'm not sure why but they need to be in

Disabled optimization in IR generation on x86 for getpc instruction sequence (call eip+5; pop xxx). 

Now VEX correctly shows it as two separate instructions.

See merge request !11

Disabled optimization in IR generation on x86 for getpc instruction sequence (call eip+5; pop xxx). Now VEX correctly shows it as two separate instructions.

x86 real mode



See merge request !10

The VexArchInfo updated in Python must be given to VEX, so we must stop
decoding new instructions if we encounter this mov, so the VEX is aware
of the potential new mode.

Now that we handle x86 real mode we must handle 16-bit address size

Small simplification to avoid duplicate computation for the handling of
LIDT/LGDT/SIDT/SGDT

Since we handle 16 bit, it should handle it also.

This register is used to handle real/protected mode. If the first bit is
0 we are in real mode, otherwise in protected mode.

the only possible are 4 and 2, so assert this

It is used everywhere in the code, so use it to be more consistent with
the code.

x86 segmentation

Handle LGDT instructions and jmp far (16 or 32 bit address)

See merge request !9

x86_toIR: handle WBINVD as nop

See merge request !8

amd64_toIR: handle CLI/STI instructions as nop

See merge request !7

{amd64,x86}_toIR: handle hlt instruction

GCC put this instruction just after the call to ___libc_start_main in
case exit failed.

In user mode this instruction will kill the process if it is executed,
but with the right privileges it will place the processor in a halt
state and can be resumed, continuing with the next instruction. Since we
cannot differentiate usermode from the other, we consider it like the
"int 0x03" debug instruction since it can be resumed the same way.

It also fixes a bug where Simuvex would have created an empty IRSB
raising an SimIRSBError.

See merge request !6

GCC put this instruction just after the call to ___libc_start_main in
case exit failed.

In user mode this instruction will kill the process if it is executed,
but with the right privileges it will place the processor in a halt
state and can be resumed, continuing with the next instruction. Since we
cannot differentiate usermode from the other, we consider it like the
"int 0x03" debug instruction since it can be resumed the same way.

It also fixes a bug where Simuvex would have created an empty IRSB
raising an SimIRSBError.

Update with upstream patches

It updates vex with all the upstream patches not currently applied except for:
- https://github.com/svn2github/valgrind-vex/commit/bce826aaab8086b1f707fd165fe52ab9710ac991
- https://github.com/svn2github/valgrind-vex/commit/8a0994cff95096eb5122e15ad8a48a774065f2ac

There was conflicts with these two patches and I was too lazy/not enough familiar with the code to fix them properly. So if someone is motivated :)

There was conflicts with https://github.com/svn2github/valgrind-vex/commit/11f435c64ca53b62855bab055c870a8f3707dd8e
and I fix them as you can see in: https://git.seclab.cs.ucsb.edu/gitlab/angr/vex/commit/1faf0ad5e57de88c396d011dab09d78c348ad684

I also needed to add Makefile rules for a new platform that has been added (TileGX).

See merge request !5

Add solaris patches from https://github.com/svn2github/valgrind-vex/commit/8a0994cff95096eb5122e15ad8a48a774065f2ac

Add mips64 patches from https://github.com/svn2github/valgrind-vex/commit/bce826aaab8086b1f707fd165fe52ab9710ac991

x86_toIR: handle CLI/STI instructions as nop

See merge request !4