/* dcache-model.c -- data cache simulation

   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
   Copyright (C) 2008 Embecosm Limited
  
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
  
   This file is part of OpenRISC 1000 Architectural Simulator.
  
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
  
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
  
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see <http://www.gnu.org/licenses/>. */

/* This program is commented throughout in a fashion suitable for processing
   with Doxygen. */

/* Cache functions.  At the moment these functions only simulate functionality
   of data caches and do not influence on fetche/decode/execute stages and
   timings.  They are here only to verify performance of various cache
   configurations. */


/* Autoconf and/or portability configuration */
#include "config.h"

/* Package includes */
#include "dcache-model.h"
#include "execute.h"
#include "spr-defs.h"
#include "abstract.h"
#include "stats.h"
#include "misc.h"
#include "pcu.h"

/* Data cache */

struct dc_set
{
  struct
  {
    uint32_t line[MAX_DC_BLOCK_SIZE/4];
    oraddr_t tagaddr;		/* tag address */
    int lru;			/* least recently used */
  } way[MAX_DC_WAYS];
} dc[MAX_DC_SETS];

void
dc_info (void)
{
  if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP))
    {
      PRINTF ("DCache not implemented. Set UPR[DCP].\n");
      return;
    }

  PRINTF ("Data cache %dKB: ",
	  config.dc.nsets * config.dc.blocksize * config.dc.nways / 1024);
  PRINTF ("%d ways, %d sets, block size %d bytes\n", config.dc.nways,
	  config.dc.nsets, config.dc.blocksize);
}


static uint32_t
dc_read_from_line (oraddr_t line_offset, int width, uint32_t *line,
		   int *read_bytes, int *next_shamt)
{
  int idx = line_offset / 4;
  int shamt = (line_offset % 4) * 8;

  uint32_t data = line[idx] >> shamt;
  if (width < 4)
    data &= (1 << (width * 8)) - 1;

  *read_bytes = width;
  *next_shamt = 0;

  if ((line_offset % width) != 0)
    {
      int first_num_bytes = sizeof(uint32_t) - (line_offset % 4);
      int second_num_bytes = width - first_num_bytes;

      int second_shamt = (width - second_num_bytes) * 8;

      if (first_num_bytes < 4)
	data &= (((uint32_t)1 << (first_num_bytes * 8)) - 1);

      if (idx + 1 < config.dc.blocksize / 4)
	{
	  data |= line[idx + 1] << second_shamt;
	  if (width < 4)
	    data &= (((uint32_t)1 << (width * 8)) - 1);
	}
      else
	{
	  *read_bytes = first_num_bytes;
	  *next_shamt = second_shamt;
	}
    }

  return data;
}

/* First check if data is already in the cache and if it is:
    - increment DC read hit stats,
    - set 'lru' at this way to config.dc.ustates - 1 and
      decrement 'lru' of other ways unless they have reached 0,
   and if not:
    - increment DC read miss stats
    - find lru way and entry and replace old tag with tag of the 'dataaddr'
    - set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
      ways unless they have reached 0
    - refill cache line
*/

uint32_t
dc_simulate_read (oraddr_t dataaddr, oraddr_t virt_addr, int width)
{
  int read_bytes = 0;
  int step_shamt = 0;
  uint32_t data = 0;

  if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP) ||
      !(cpu_state.sprs[SPR_SR] & SPR_SR_DCE) || data_ci)
    {
      if (width == 4)
	data = evalsim_mem32 (dataaddr, virt_addr);
      else if (width == 2)
	data = evalsim_mem16 (dataaddr, virt_addr);
      else if (width == 1)
	data = evalsim_mem8 (dataaddr, virt_addr);

      if (cur_area && cur_area->log)
	fprintf (cur_area->log, "[%" PRIxADDR "] -> read %08" PRIx32 "\n",
		 dataaddr, data);

      return data;
    }

  while (read_bytes < width)
    {
      int next_shamt, nbytes;
      int set, way = -1;
      int i;
      uint32_t *line;
      uint32_t tmp;
      oraddr_t tagaddr;

      /* Which set to check out? */
      set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
      tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;

      /* Scan all ways and try to find a matching way. */
      for (i = 0; i < config.dc.nways; i++)
	if (dc[set].way[i].tagaddr == tagaddr)
	  way = i;

      /* Did we find our cached data? */
      if (way >= 0)
	{				/* Yes, we did. */
	  dc_stats.readhit++;

	  for (i = 0; i < config.dc.nways; i++)
	    if (dc[set].way[i].lru > dc[set].way[way].lru)
	      dc[set].way[i].lru--;
	  dc[set].way[way].lru = config.dc.ustates - 1;
	  runtime.sim.mem_cycles += config.dc.load_hitdelay;
	  line = dc[set].way[way].line;
	}
      else
	{				/* No, we didn't. */
	  int minlru = config.dc.ustates - 1;
	  int minway = 0;

	  dc_stats.readmiss++;

	  for (i = 0; i < config.dc.nways; i++)
	    {
	      if (dc[set].way[i].lru < minlru)
		{
		  minway = i;
		  minlru = dc[set].way[i].lru;
		}
	    }

	  for (i = 0; i < (config.dc.blocksize); i += 4)
	    {
	      /* FIXME: What is the virtual address meant to be? (ie. What happens if
	       * we read out of memory while refilling a cache line?) */
	      tmp =
		evalsim_mem32 ((dataaddr & ~(config.dc.blocksize - 1)) +
			       (((dataaddr & ~ADDR_C (3)) +
				 i) & (config.dc.blocksize - 1)), 0);

	      dc[set].way[minway].
		line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] = tmp;
	      if (!cur_area)
		{
		  dc[set].way[minway].tagaddr = -1;
		  dc[set].way[minway].lru = 0;
		  return 0;
		}
	      else if (cur_area->log)
		fprintf (cur_area->log, "[%" PRIxADDR "] -> read %08" PRIx32 "\n",
			 dataaddr, tmp);
	    }

	  dc[set].way[minway].tagaddr = tagaddr;
	  for (i = 0; i < config.dc.nways; i++)
	    if (dc[set].way[i].lru)
	      dc[set].way[i].lru--;
	  dc[set].way[minway].lru = config.dc.ustates - 1;
	  runtime.sim.mem_cycles += config.dc.load_missdelay;

	  if (config.pcu.enabled)
	    pcu_count_event(SPR_PCMR_DCM);

	  line = dc[set].way[minway].line;
	}

      tmp = dc_read_from_line (dataaddr & (config.dc.blocksize - 1),
			       width - read_bytes, line, &nbytes, &next_shamt);
      tmp <<= step_shamt;
      data |= tmp;

      dataaddr += nbytes;
      read_bytes += nbytes;
      step_shamt += next_shamt;

    }
  return data;
}

static void
dc_write_to_line (oraddr_t line_offset, int width, uint32_t data,
		  uint32_t *line, int *written_bytes, int *next_shamt)
{
  int idx = line_offset / 4;
  int shamt = (line_offset % 4) * 8;

  uint32_t mask = ((uint32_t)1 << shamt) - 1;

  if (shamt + 8 * width < 32)
   mask |= ((uint32_t)(-1) << (shamt + 8 * width));

  uint32_t newdata = (line[idx] & mask) | ((data << shamt) & ~mask);
  line[idx] = newdata;

  *written_bytes = width;
  *next_shamt = width * 8;

  if ((line_offset % width) != 0)
    {
      int first_num_bytes = sizeof(uint32_t) - (line_offset % 4);
      int second_num_bytes = width - first_num_bytes;

      int data_shamt = first_num_bytes * 8;
      int second_shamt = second_num_bytes * 8;
      uint32_t second_mask = ((uint32_t)1 << second_shamt) - 1;

      if (idx + 1 < config.dc.blocksize / 4)
	{
	  uint32_t newdata = (line[idx + 1] & ~second_mask) |
			     ((data >> data_shamt) & second_mask);
	  line[idx + 1] = newdata;
	}
      else
	{
	  *written_bytes = first_num_bytes;
	  *next_shamt = first_num_bytes * 8;
	}
    }
}

/* First check if data is already in the cache and if it is:
    - increment DC write hit stats,
    - set 'lru' at this way to config.dc.ustates - 1 and
      decrement 'lru' of other ways unless they have reached 0,
   and if not:
    - increment DC write miss stats
    - find lru way and entry and replace old tag with tag of the 'dataaddr'
    - set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
      ways unless they have reached 0
*/

void
dc_simulate_write (oraddr_t dataaddr, oraddr_t virt_addr, uint32_t data,
		   int width)
{
  int written_bytes = 0;

  if (width == 4)
    setsim_mem32 (dataaddr, virt_addr, data);
  else if (width == 2)
    setsim_mem16 (dataaddr, virt_addr, data);
  else if (width == 1)
    setsim_mem8 (dataaddr, virt_addr, data);

  if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP) ||
      !(cpu_state.sprs[SPR_SR] & SPR_SR_DCE) || data_ci || !cur_area)
    return;

  while (written_bytes < width)
    {
      int next_shamt, nbytes;
      int set, way = -1;
      int i;
      oraddr_t tagaddr;
      uint32_t *line;

      /* Which set to check out? */
      set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
      tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;

      /* Scan all ways and try to find a matching way. */
      for (i = 0; i < config.dc.nways; i++)
	if (dc[set].way[i].tagaddr == tagaddr)
	  way = i;

      /* Did we find our cached data? */
      if (way >= 0)
	{				/* Yes, we did. */
	  dc_stats.writehit++;

	  for (i = 0; i < config.dc.nways; i++)
	    if (dc[set].way[i].lru > dc[set].way[way].lru)
	      dc[set].way[i].lru--;
	  dc[set].way[way].lru = config.dc.ustates - 1;
	  runtime.sim.mem_cycles += config.dc.store_hitdelay;

	  line = dc[set].way[way].line;
	}
      else
	{				/* No, we didn't. */
	  int minlru = config.dc.ustates - 1;
	  int minway = 0;

	  dc_stats.writemiss++;

	  for (i = 0; i < config.dc.nways; i++)
	    if (dc[set].way[i].lru < minlru)
	      minway = i;

	  for (i = 0; i < (config.dc.blocksize); i += 4)
	    {
	      dc[set].way[minway].
		line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
		/* FIXME: Same comment as in dc_simulate_read */
		evalsim_mem32 ((dataaddr & ~(config.dc.blocksize - 1)) +
			       (((dataaddr & ~3ul) + i) & (config.dc.blocksize -
							   1)), 0);
	      if (!cur_area)
		{
		  dc[set].way[minway].tagaddr = -1;
		  dc[set].way[minway].lru = 0;
		  return;
		}
	    }

	  dc[set].way[minway].tagaddr = tagaddr;
	  for (i = 0; i < config.dc.nways; i++)
	    if (dc[set].way[i].lru)
	      dc[set].way[i].lru--;
	  dc[set].way[minway].lru = config.dc.ustates - 1;
	  runtime.sim.mem_cycles += config.dc.store_missdelay;

	  if (config.pcu.enabled)
	    pcu_count_event(SPR_PCMR_DCM);

	  line = dc[set].way[minway].line;
	}

      dc_write_to_line(dataaddr & (config.dc.blocksize - 1),
		       width - written_bytes, data, line, &nbytes,
		       &next_shamt);

      data >>= next_shamt;
      dataaddr += nbytes;
      written_bytes += nbytes;
    }
}

/* First check if data is already in the cache and if it is:
    - invalidate block if way isn't locked
   otherwise don't do anything.
*/

void
dc_inv (oraddr_t dataaddr)
{
  int set, way = -1;
  int i;
  oraddr_t tagaddr;

  if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP))
    return;

  /* Which set to check out? */
  set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
  tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;

  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DCE))
    {
      for (i = 0; i < config.dc.nways; i++)
	{
	  dc[set].way[i].tagaddr = -1;
	  dc[set].way[i].lru = 0;
	}
      return;
    }
  /* Scan all ways and try to find a matching way. */
  for (i = 0; i < config.dc.nways; i++)
    if (dc[set].way[i].tagaddr == tagaddr)
      way = i;

  /* Did we find our cached data? */
  if (way >= 0)
    {				/* Yes, we did. */
      dc[set].way[way].tagaddr = -1;
      dc[set].way[way].lru = 0;
    }
}

/*-----------------------------------------------------[ DC configuration ]---*/

/*---------------------------------------------------------------------------*/
/*!Enable or disable the data cache

   Set the corresponding field in the UPR

   @param[in] val  The value to use
   @param[in] dat  The config data structure (not used here)                 */
/*---------------------------------------------------------------------------*/
static void
dc_enabled (union param_val  val,
	    void            *dat)
{
  if (val.int_val)
    {
      cpu_state.sprs[SPR_UPR] |= SPR_UPR_DCP;
    }
  else
    {
      cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DCP;
    }

  config.dc.enabled = val.int_val;

    }	/* dc_enabled() */


/*---------------------------------------------------------------------------*/
/*!Set the number of data cache sets

   Value must be a power of 2 <= MAX_DC_SETS. If not issue a warning and
   ignore. Set the relevant field in the data cache config register

   @param[in] val  The value to use
   @param[in] dat  The config data structure (not used here)                 */
/*---------------------------------------------------------------------------*/
static void
dc_nsets (union param_val  val,
	  void            *dat)
{
  if (is_power2 (val.int_val) && (val.int_val <= MAX_DC_SETS))
    {
      int  set_bits = log2_int (val.int_val);

      config.dc.nsets = val.int_val;

      cpu_state.sprs[SPR_DCCFGR] &= ~SPR_DCCFGR_NCS;
      cpu_state.sprs[SPR_DCCFGR] |= set_bits << SPR_DCCFGR_NCS_OFF;
    }
  else
    {
      fprintf (stderr, "Warning: data cache nsets not a power of 2 <= %d: "
	       "ignored\n", MAX_DC_SETS);
    }
}	/* dc_nsets() */


/*---------------------------------------------------------------------------*/
/*!Set the number of data cache ways

   Value must be a power of 2 <= MAX_DC_WAYS. If not issue a warning and
   ignore. Set the relevant field in the data cache config register

   @param[in] val  The value to use
   @param[in] dat  The config data structure (not used here)                 */
/*---------------------------------------------------------------------------*/
static void
dc_nways (union param_val  val,
	  void            *dat)
{
  if (is_power2 (val.int_val) && (val.int_val <= MAX_DC_WAYS))
    {
      int  way_bits = log2_int (val.int_val);

      config.dc.nways = val.int_val;

      cpu_state.sprs[SPR_DCCFGR] &= ~SPR_DCCFGR_NCW;
      cpu_state.sprs[SPR_DCCFGR] |= way_bits << SPR_DCCFGR_NCW_OFF;
    }
  else
    {
      fprintf (stderr, "Warning: data cache nways not a power of 2 <= %d: "
	       "ignored\n", MAX_DC_WAYS);
    }
}	 /* dc_nways() */


/*---------------------------------------------------------------------------*/
/*!Set the data cache block size

   Value must be either MIN_DC_BLOCK_SIZE or MAX_DC_BLOCK_SIZE. If not issue a
   warning and ignore. Set the relevant field in the data cache config register

   @param[in] val  The value to use
   @param[in] dat  The config data structure (not used here)                 */
/*---------------------------------------------------------------------------*/
static void
dc_blocksize (union param_val  val,
	      void            *dat)
{
  switch (val.int_val)
    {
    case MIN_DC_BLOCK_SIZE:
      config.dc.blocksize         = val.int_val;
      cpu_state.sprs[SPR_DCCFGR] &= ~SPR_DCCFGR_CBS;
      break;

    case MAX_DC_BLOCK_SIZE:
      config.dc.blocksize         = val.int_val;
      cpu_state.sprs[SPR_DCCFGR] |= SPR_DCCFGR_CBS;
      break;

    default:
      fprintf (stderr, "Warning: data cache block size not %d or %d: "
	       "ignored\n", MIN_DC_BLOCK_SIZE, MAX_DC_BLOCK_SIZE);
      break;
    }
}	/* dc_blocksize() */


/*---------------------------------------------------------------------------*/
/*!Set the number of data cache usage states

   Value must be 2, 3 or 4. If not issue a warning and ignore.

   @param[in] val  The value to use
   @param[in] dat  The config data structure (not used here)                 */
/*---------------------------------------------------------------------------*/
static void
dc_ustates (union param_val  val,
	    void            *dat)
{
  if ((val.int_val >= 2) && (val.int_val <= 4))
    {
      config.dc.ustates = val.int_val;
    }
  else
    {
      fprintf (stderr, "Warning number of data cache usage states must be "
	       "2, 3 or 4: ignored\n");
    }
}	/* dc_ustates() */


static void
dc_load_hitdelay (union param_val val, void *dat)
{
  config.dc.load_hitdelay = val.int_val;
}

static void
dc_load_missdelay (union param_val val, void *dat)
{
  config.dc.load_missdelay = val.int_val;
}

static void
dc_store_hitdelay (union param_val val, void *dat)
{
  config.dc.store_hitdelay = val.int_val;
}

static void
dc_store_missdelay (union param_val val, void *dat)
{
  config.dc.store_missdelay = val.int_val;
}

void
reg_dc_sec (void)
{
  struct config_section *sec = reg_config_sec ("dc", NULL, NULL);

  reg_config_param (sec, "enabled",         PARAMT_INT, dc_enabled);
  reg_config_param (sec, "nsets",           PARAMT_INT, dc_nsets);
  reg_config_param (sec, "nways",           PARAMT_INT, dc_nways);
  reg_config_param (sec, "blocksize",       PARAMT_INT, dc_blocksize);
  reg_config_param (sec, "ustates",         PARAMT_INT, dc_ustates);
  reg_config_param (sec, "load_hitdelay",   PARAMT_INT, dc_load_hitdelay);
  reg_config_param (sec, "load_missdelay",  PARAMT_INT, dc_load_missdelay);
  reg_config_param (sec, "store_hitdelay",  PARAMT_INT, dc_store_hitdelay);
  reg_config_param (sec, "store_missdelay", PARAMT_INT, dc_store_missdelay);
}
