From df9024760efa9a32e24629eb80665c8c4ec5f145 Mon Sep 17 00:00:00 2001
From: Richard Henderson <richard.henderson@linaro.org>
Date: Fri, 27 May 2022 11:18:59 -0700
Subject: [PATCH] target/arm: Remove assert in trans_FCMLA_zzxz
Since 636ddeb15c0, we do not require rd == ra.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-107-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-sve.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 886cf539a52..436d09b928a 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4027,8 +4027,6 @@ static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a)
NULL,
};
- tcg_debug_assert(a->rd == a->ra);
-
return gen_gvec_fpst_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra,
a->index * 4 + a->rot,
a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
--
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