diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index dbe58c7888f73422af15260aace6568ac9b684a2..714e3b5641339d0ac2814ddc35f8f0897bd237e8 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -160,7 +160,7 @@ typedef struct CPUSH4State {
     uint32_t pteh;		/* page table entry high register */
     uint32_t ptel;		/* page table entry low register */
     uint32_t ptea;		/* page table entry assistance register */
-    uint32_t ttb;		/* tranlation table base register */
+    uint32_t ttb;               /* translation table base register */
     uint32_t tea;		/* TLB exception address register */
     uint32_t tra;		/* TRAPA exception register */
     uint32_t expevt;		/* exception event register */
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
index fcd9ac7271c62ee604208d0b6a14b92e910e677c..c0cbb95382878c3abe0df6e26cef320464a52c01 100644
--- a/target/sh4/op_helper.c
+++ b/target/sh4/op_helper.c
@@ -401,7 +401,7 @@ float32 helper_fsrra_FT(CPUSH4State *env, float32 t0)
     /*
      * Since this is supposed to be an approximation, an imprecision
      * exception is required.  One supposes this also follows the usual
-     * IEEE rule that other exceptions take precidence.
+     * IEEE rule that other exceptions take precedence.
      */
     if (get_float_exception_flags(&env->fp_status) == 0) {
         set_float_exception_flags(float_flag_inexact, &env->fp_status);
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index ec5b04889e19145fb6c1d9f97cf483b3406d640b..9312790623730b76b147ddfd765b5cf603379155 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -1960,7 +1960,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
     switch (ctx->opcode & 0xf00f) {
     case 0x6003: /* mov Rm,Rn */
         /*
-         * Here we want to recognize ld_dst being saved for later consumtion,
+         * Here we want to recognize ld_dst being saved for later consumption,
          * or for another input register being copied so that ld_dst need not
          * be clobbered during the operation.
          */